Design of a Multi-Core Scheduling Scheme for Tera-bit/s LDPC Decoding

Abstract

$A$ scheduling scheme for multi-core Low-Density Parity-Check (LDPC) decoding is proposed to make full use of logical resources and to maximize the decoding throughput in the high-speed communication systems. In the proposed scheme, consecutive code blocks are processed in different decoding cores according to a variable allocation sequence which is decided by the parity checking result of the decoding sequence. And the scheme is mathematically analyzed with the Gaussian approximation analyzing algorithm and the Sum-Product Algorithm (SPA). It is shown that the proposed scheme can improve the decoding throughput by up to 130% compared to the conventional multicore parallel architectures.