Kangmin Lee, Se-Joong Lee, Sung-Eun Kim, Hye-Mi Choi, Donghyun Kim, Sunyoung Kim, Min-wuk Lee, H. Yoo
{"title":"A 51mW 1.6GHz on-chip network for low-power heterogeneous SoC platform","authors":"Kangmin Lee, Se-Joong Lee, Sung-Eun Kim, Hye-Mi Choi, Donghyun Kim, Sunyoung Kim, Min-wuk Lee, H. Yoo","doi":"10.1109/ISSCC.2004.1332639","DOIUrl":null,"url":null,"abstract":"A 1.6GHz on-chip network integrating two processors, memories, and an FPGA provides 11.2GB/s bandwidth in 0.18/spl mu/m 6M CMOS technology. The 2-level hierarchical star-connected network using serialized low-energy transmission coding, crossbar partial activation and lowswing signaling dissipates 51 mW at 1.6V supporting globally asynchronous, locally synchronous mode and programmable clocking.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"104","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2004.1332639","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 104
Abstract
A 1.6GHz on-chip network integrating two processors, memories, and an FPGA provides 11.2GB/s bandwidth in 0.18/spl mu/m 6M CMOS technology. The 2-level hierarchical star-connected network using serialized low-energy transmission coding, crossbar partial activation and lowswing signaling dissipates 51 mW at 1.6V supporting globally asynchronous, locally synchronous mode and programmable clocking.
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