Instruction based bist for board/system level test of external memories and internconnects

Abstract

This paper describes a general technique to test external memory/caches and memory interconnects using on-chip logic. Such a test methodology is expected to significantly reduce boardhystem manufacturing test cost as well as to improve diagnosability of memory and memory-interconnect failures. The proposed methodology incorporates a significant amount of programmability (including programmable MARCH algorithms and data backgrounds) to enable proper testing of all diflerentjavors of memories and caches that one encounters in systems today. Another important aspect of the methodology is its reuse of on-chip memorykache controllers. This allows the adaptation of the methodology to a variety of memory access protocols (including DDR), without having to re-implement the access protocol inside the BIST engine. These considerations make the External BIST methodology presented in the papei; very general and adaptable to a wide range of applications and their corresponding memory sub-systems.