T. Arakawa, M. Ueda, Y. Saito, T. Fujimura, S. Asai, M. Terai, Y. Akasaka, Y. Kuramitsu
{"title":"A basic-cell buffer 440K-transistor CMOS masterslice","authors":"T. Arakawa, M. Ueda, Y. Saito, T. Fujimura, S. Asai, M. Terai, Y. Akasaka, Y. Kuramitsu","doi":"10.1109/ISSCC.1986.1156920","DOIUrl":null,"url":null,"abstract":"A masterslice containing 437,976 transistors on a 12.7×11.96mm2chip and employing a gate-isolation concept with no fixed routing tracks and no dedicated buffers, will be reported. The masterslice has been fabricated in 1.3μm CMOS technology. A 13MHz facsimile processor has been implemented using this array.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1986.1156920","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A masterslice containing 437,976 transistors on a 12.7×11.96mm2chip and employing a gate-isolation concept with no fixed routing tracks and no dedicated buffers, will be reported. The masterslice has been fabricated in 1.3μm CMOS technology. A 13MHz facsimile processor has been implemented using this array.
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