Stress evaluations in Micro Bump structures of FCBGA

Abstract

System in Package(SiP) includes technologies of Multi-chip Module(MCM), Multi-chip Package(MCP), stacked die, Package on Package(PoP), Package in Package(PiP) and Embedded substrate. While Au wire bonding technology is commonly used as current SIP interconnection solution, take Staked Die structure for example, with increasing stack die number upper die needs longer wire bonding length for signal interconnection and results in lower electrical performance for whole system. In addition, wire bonding technology as Stacked die solution requires spacer die insertion between functional chips for bonding space and thus increases total package thickness. In order to achieve better electrical performance and reduce form factor, a new fine pitch bump technology of “Micro Bump” structure is developed with metal bump for both top and bottom chips. Micro bump structure is one of the key technologies of Trough Silicon Vias (TSV) and is used in chip to chip interconnection with the dimension of Micro bump smaller than typical flip chip bump. In this study a 15mm×15mm Face-to-Face Stacked-die Thin and Fine-pitch BGA (F2F-STFBGA) package was adopted for Finite Element Method (FEM) analysis. The evaluations focused on low-k stress, bump stress and pad peeling stress of different Micro Bump structures. Firstly two different face to face interconnection levels of chip to chip and chip to substrate (EHS-FCBGA) were investigated. Secondly four different interconnection bump structures of common bump structure (solder bump), Cu pillar for both top and bottom bump, Cu pillar for both top bump and Au for bottom bump, Au for top bump and Cu pillar for bottom bump were compared. In conclusion a design guideline of F2F-S2TFBGA package was recommended with considerations of Micro Bump structure, material, and package geometry.