Impact of oxide thickness variation on the performance of junctionless FinFET

Abstract

The relentless advances in the complementary metal oxide semiconductor (CMOS) technology have mainly enabled through dimensional downscaling of the transistor which brings out numerous challenges such as controlling short channel effects (SCEs), leakage current and fabrication complexity of forming high-quality metallurgical junction at sub-nanoscale regime. Junctionless (JL) concept in the transistor has emerged recently and shown tremendous potential for the future technology generation. It not only simplified the fabrication process but also provided the comparable performance to those of conventional junction-based metal oxide semiconductor (MOS) devices. This work, for the first time, demonstrates the impact of oxide thickness variation (OTV) on a 14 nm junctionless FinFET (JL FinFET) using extensive technology computer-aided design (TCAD) device simulation. Results show that the deviation in threshold voltage and OFF-current are seriously impacted by OTV for JL FinFET structure as compared to the normal inversion mode (IM) counterparts. Furthermore, the joint impact of all the intrinsic statistical variability sources including OTV, random dopant fluctuation (RDF) and gate work function variation (WFV) on threshold voltage has been investigated.