A Sharable Built-in Self-repair for Semiconductor Memories with 2-D Redundancy Scheme

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) Pub Date : 2007-09-26 DOI:10.1109/DFT.2007.28

Swapnil Bahl

引用次数: 26

Abstract

Newer technologies like 90 nm and 65 nm bring with them new challenges: longer time to process maturity, higher defect densities and poorer yields. The quality of test and repair determines the design's final yield and profitability. With increasing amount of memory on the chip, the need for an efficient and fast converging perfect algorithm for memory repair is increasing becoming important. In this paper, a perfect algorithm is presented for standalone repairable memories as well as for situations where redundancy is shared between different memories. The proposed BISR is composed of Built-in self-test (BIST) and built-in redundancy analysis (BIRA) module. The BISR module has a low overhead - about 5.05 % of memories area for a typical automotive chip. The proper redundancy scheme and the proposed BIRA algorithm ensure a high repair rate for the SOC and shorter test times as well as optimized area and maximum performance.

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二维冗余半导体存储器的可共享内置自修复

像90纳米和65纳米这样的新技术带来了新的挑战:更长的工艺成熟时间，更高的缺陷密度和更低的产量。测试和修复的质量决定了设计的最终成品率和盈利能力。随着芯片内存储量的不断增加，对一种高效、快速收敛的完美内存修复算法的需求变得越来越重要。本文提出了一种适用于独立可修复存储器以及不同存储器之间共享冗余的完美算法。该系统由内置自检(BIST)和内置冗余分析(BIRA)模块组成。BISR模块开销低，约为典型汽车芯片内存面积的5.05%。适当的冗余方案和提出的BIRA算法确保了SOC的高修复率和更短的测试时间，以及优化的面积和最大性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)

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