Soumya Krishnapuram Sireesh, Sanaz Hadipour Abkenar, N. Christoffers, C. Wagner, A. Stelzer
{"title":"Direct Digital Modulation and RFDAC for Generation of Frequency Ramps in FMCW Radar","authors":"Soumya Krishnapuram Sireesh, Sanaz Hadipour Abkenar, N. Christoffers, C. Wagner, A. Stelzer","doi":"10.1109/ICMIM.2019.8726843","DOIUrl":null,"url":null,"abstract":"The frequency chirps applied in frequency modulated continuous wave (FMCW) radars are typically generated using a PLL imposing trade-offs between noise and modulation accuracy. We are removing this compromise by employing a fixed frequency PLL, direct digital chirps generation and up-conversion to RF using an RFDAC. With a simplified PLL requirement and better exploitation of nm-scale CMOS digital performance, we achieve lower noise, less chip area, and frequency error, and remove the issues with frequency ramp non-linearities in conventional FMCW architectures.","PeriodicalId":225972,"journal":{"name":"2019 IEEE MTT-S International Conference on Microwaves for Intelligent Mobility (ICMIM)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE MTT-S International Conference on Microwaves for Intelligent Mobility (ICMIM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMIM.2019.8726843","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The frequency chirps applied in frequency modulated continuous wave (FMCW) radars are typically generated using a PLL imposing trade-offs between noise and modulation accuracy. We are removing this compromise by employing a fixed frequency PLL, direct digital chirps generation and up-conversion to RF using an RFDAC. With a simplified PLL requirement and better exploitation of nm-scale CMOS digital performance, we achieve lower noise, less chip area, and frequency error, and remove the issues with frequency ramp non-linearities in conventional FMCW architectures.