{"title":"Analyzing internal-switching induced simultaneous switching noise","authors":"Li Yang, J. Yuan","doi":"10.1109/ISQED.2003.1194768","DOIUrl":null,"url":null,"abstract":"The internal-switching induced simultaneous switching noise (SSN) is studied in the paper. Unlike ground bounce caused by driving off-chip loading, both power-rail and ground-rail wire/pin impedances are important in evaluating internal SSN, and the double negative feedback mechanism should be accounted for. Based on the lumped-model analysis and taking into account the parasitic effects and velocity-saturation effect of MOS transistors, a novel analytical model is developed which includes both switching and non-switching gates. The proposed model is employed to analyze on-chip decoupling capacitance, wire/pin inductance effect and loading effect analytically. Good agreements with SPICE simulations are obtained for submicron technology.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2003.1194768","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
The internal-switching induced simultaneous switching noise (SSN) is studied in the paper. Unlike ground bounce caused by driving off-chip loading, both power-rail and ground-rail wire/pin impedances are important in evaluating internal SSN, and the double negative feedback mechanism should be accounted for. Based on the lumped-model analysis and taking into account the parasitic effects and velocity-saturation effect of MOS transistors, a novel analytical model is developed which includes both switching and non-switching gates. The proposed model is employed to analyze on-chip decoupling capacitance, wire/pin inductance effect and loading effect analytically. Good agreements with SPICE simulations are obtained for submicron technology.
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