Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194736
Michael X. Wang, Katsuharu Suzuki, W. Dai
This paper presents an electrical and thermal performance analysis of system-in-a-package (SiP) memory/logic implementation platform based on chip-laminate-chip (CLC) technology. Internal IO interface inside CLC module has been modeled and compared with stack-chip (SC) implementation. Thermal analysis, including comparison against stack-chip and system-on- a-chip (SoC) is also presented. It is demonstrated that CLC technology provides significant performance advantage over conventional SiP technologies and has great impact on future system-level integration.
{"title":"Electrical and thermal analysis for system-in-a package (SiP) implementation platform","authors":"Michael X. Wang, Katsuharu Suzuki, W. Dai","doi":"10.1109/ISQED.2003.1194736","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194736","url":null,"abstract":"This paper presents an electrical and thermal performance analysis of system-in-a-package (SiP) memory/logic implementation platform based on chip-laminate-chip (CLC) technology. Internal IO interface inside CLC module has been modeled and compared with stack-chip (SC) implementation. Thermal analysis, including comparison against stack-chip and system-on- a-chip (SoC) is also presented. It is demonstrated that CLC technology provides significant performance advantage over conventional SiP technologies and has great impact on future system-level integration.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116033735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194728
Xiaoliang Bai, R. Chandra, S. Dey, P. V. Srinivas
With the semiconductor industry evolving into the deep sub-micron (DSM) era, crosstalk noise becomes a critical issue that needs to be handled efficiently and accurately. Modern designs like system-on-chips have millions of noise-prone wires that need to be analyzed. Analysis using circuit-level simulation is not feasible. Efficient static noise analysis, which statically estimate noise based on linear circuit model, is widely used. However, traditionally drivers' holding resistances are pre-characterized without considering the crosstalk noise. The driver's holding resistance changes dramatically with the crosstalk noise induced voltage changing on the victim wire. For accurate noise estimation, the driver's substantial nonlinear variation cannot be ignored. In this paper, we propose a novel method, which uses layout extracted parameters of coupling interconnect and pre-characterized parameters of driver to calculate an effective holding resistance. The noise-aware effective holding resistance dramatically improves the accuracy for noise magnitude and energy estimation. The proposed method is simple and efficient. It enables fast on-the-fly calculation of the effective holding resistance. Experiments show significant improvement in accuracy with almost negligible computation overhead.
{"title":"Noise-aware driver modeling for nanometer technology","authors":"Xiaoliang Bai, R. Chandra, S. Dey, P. V. Srinivas","doi":"10.1109/ISQED.2003.1194728","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194728","url":null,"abstract":"With the semiconductor industry evolving into the deep sub-micron (DSM) era, crosstalk noise becomes a critical issue that needs to be handled efficiently and accurately. Modern designs like system-on-chips have millions of noise-prone wires that need to be analyzed. Analysis using circuit-level simulation is not feasible. Efficient static noise analysis, which statically estimate noise based on linear circuit model, is widely used. However, traditionally drivers' holding resistances are pre-characterized without considering the crosstalk noise. The driver's holding resistance changes dramatically with the crosstalk noise induced voltage changing on the victim wire. For accurate noise estimation, the driver's substantial nonlinear variation cannot be ignored. In this paper, we propose a novel method, which uses layout extracted parameters of coupling interconnect and pre-characterized parameters of driver to calculate an effective holding resistance. The noise-aware effective holding resistance dramatically improves the accuracy for noise magnitude and energy estimation. The proposed method is simple and efficient. It enables fast on-the-fly calculation of the effective holding resistance. Experiments show significant improvement in accuracy with almost negligible computation overhead.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"14 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116813241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194751
D. Stefanovic, M. Kayal, M. Pastre, V. Litovski
This paper presents a new procedural analog design tool called PAD. It is a chart-based design environment dedicated to the design of analog circuits aiming to optimise design and quality by finding good tradeoffs. This interactive tool allows step-by-step design of analog cells by using guidelines for each analog topology. At each step, the user modifies interactively one subset of design parameters and observes the effect on other circuit parameters. At the end, an optimised design is ready for simulation (verification and fine-tuning). Furthermore, PAD provides a layout generator for matched substructures such as current mirror, cascode stage, differential pair, etc. The analog basic structures calculator embedded in PAD uses the complete set of equations of the EKV MOS model, which links the equations for weak and strong inversion in a continuous way. The present version of PAD covers the procedural design of transconductance amplifiers (OTAs) and different operational amplifiers topologies.
{"title":"Procedural analog design (PAD) tool","authors":"D. Stefanovic, M. Kayal, M. Pastre, V. Litovski","doi":"10.1109/ISQED.2003.1194751","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194751","url":null,"abstract":"This paper presents a new procedural analog design tool called PAD. It is a chart-based design environment dedicated to the design of analog circuits aiming to optimise design and quality by finding good tradeoffs. This interactive tool allows step-by-step design of analog cells by using guidelines for each analog topology. At each step, the user modifies interactively one subset of design parameters and observes the effect on other circuit parameters. At the end, an optimised design is ready for simulation (verification and fine-tuning). Furthermore, PAD provides a layout generator for matched substructures such as current mirror, cascode stage, differential pair, etc. The analog basic structures calculator embedded in PAD uses the complete set of equations of the EKV MOS model, which links the equations for weak and strong inversion in a continuous way. The present version of PAD covers the procedural design of transconductance amplifiers (OTAs) and different operational amplifiers topologies.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129911424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194716
Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, N. Mukherjee, S. Reddy
An algorithm for mapping core terminals to system-on-a-chip (SOC) I/O pins and scheduling tests in order to achieve cost-efficient concurrent test for core-based designs is presented in this paper. In this work "static" pin mapping and test scheduling for concurrent testing are studied for the case of multiple test sets for each core. The problem is formulated as a constrained two-dimensional bin-packing problem. A heuristic algorithm is then proposed to determine a solution. The objectives driving this solution are geared towards reducing the total test application time of SOC and satisfying the test constraints such as limited number of SOC pins and maximum peak power dissipation specified by core integrators. Experimental results demonstrate the effectiveness of the proposed method.
{"title":"Static pin mapping and SOC test scheduling for cores with multiple test sets","authors":"Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, N. Mukherjee, S. Reddy","doi":"10.1109/ISQED.2003.1194716","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194716","url":null,"abstract":"An algorithm for mapping core terminals to system-on-a-chip (SOC) I/O pins and scheduling tests in order to achieve cost-efficient concurrent test for core-based designs is presented in this paper. In this work \"static\" pin mapping and test scheduling for concurrent testing are studied for the case of multiple test sets for each core. The problem is formulated as a constrained two-dimensional bin-packing problem. A heuristic algorithm is then proposed to determine a solution. The objectives driving this solution are geared towards reducing the total test application time of SOC and satisfying the test constraints such as limited number of SOC pins and maximum peak power dissipation specified by core integrators. Experimental results demonstrate the effectiveness of the proposed method.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128384210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194759
M. Ker, Hsin-Chyh Hsu, Jeng-Jie Peng
A novel electrostatic discharge (ESD) implantation method is proposed to significantly improve machine-model (MM) ESD robustness of NMOS device in stacked configuration (stacked NMOS). By using this ESD implantation method, the ESD current is discharged far away from the surface channel of NMOS, therefore the stacked NMOS in the mixed-voltage I/O interface can sustain a much higher ESD level, especially under the MM ESD stress. The MM ESD robustness of the stacked NMOS with a device dimension of W/L=300 /spl mu/m/0.5 /spl mu/m for each NMOS has been successfully improved from the original 358 V to become 491 V in a 0.25 /spl mu/m CMOS process. This ESD implantation method with the n-type impurity is fully process-compatible to general sub-quarter-micron CMOS processes.
{"title":"Electrostatic discharge implantation to improve machine-model ESD robustness of stacked NMOS in mixed I/O interface circuits","authors":"M. Ker, Hsin-Chyh Hsu, Jeng-Jie Peng","doi":"10.1109/ISQED.2003.1194759","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194759","url":null,"abstract":"A novel electrostatic discharge (ESD) implantation method is proposed to significantly improve machine-model (MM) ESD robustness of NMOS device in stacked configuration (stacked NMOS). By using this ESD implantation method, the ESD current is discharged far away from the surface channel of NMOS, therefore the stacked NMOS in the mixed-voltage I/O interface can sustain a much higher ESD level, especially under the MM ESD stress. The MM ESD robustness of the stacked NMOS with a device dimension of W/L=300 /spl mu/m/0.5 /spl mu/m for each NMOS has been successfully improved from the original 358 V to become 491 V in a 0.25 /spl mu/m CMOS process. This ESD implantation method with the n-type impurity is fully process-compatible to general sub-quarter-micron CMOS processes.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122281982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194708
A. Abdollahi, F. Fallah, Massoud Pedram
Input vector control is an effective technique for reducing the leakage current of combinational VLSI circuits when these circuits are in the sleep mode. In this paper a design technique for applying the minimum leakage input to a sequential circuit is proposed. Our method uses the built-in scan-chain in a VLSI circuit to drive it with the minimum leakage vector when it enters the sleep mode. Using these scan registers eliminates the area and delay overhead of the additional circuitry that would otherwise be needed to apply the minimum leakage vector to the circuit. We show how the proposed technique can be used for several different scan-chain architectures and present the experimental results on the MCNC91 benchmark circuits.
{"title":"Leakage current reduction in sequential circuits by modifying the scan chains","authors":"A. Abdollahi, F. Fallah, Massoud Pedram","doi":"10.1109/ISQED.2003.1194708","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194708","url":null,"abstract":"Input vector control is an effective technique for reducing the leakage current of combinational VLSI circuits when these circuits are in the sleep mode. In this paper a design technique for applying the minimum leakage input to a sequential circuit is proposed. Our method uses the built-in scan-chain in a VLSI circuit to drive it with the minimum leakage vector when it enters the sleep mode. Using these scan registers eliminates the area and delay overhead of the additional circuitry that would otherwise be needed to apply the minimum leakage vector to the circuit. We show how the proposed technique can be used for several different scan-chain architectures and present the experimental results on the MCNC91 benchmark circuits.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134103791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194752
M. Mansour, Mohammad M. Mansour, A. Mehrotra
In this paper we propose a new design methodology targeted for core-based designs using parameterized macrocells (PMC's). This methodology provides the flexibility for instance-based cores to be easily customized for application requirements. By using few scaling parameters to characterize a PMC, a macrocell can be instantiated in virtually any size depending on the required performance. Moreover a new first-order macro delay model is proposed which is a function of the scaling parameters of the PMC which enables accurate delay predictions at the subsystem/core level. The proposed delay model is suitable for use by a delay optimizer to determine the optimum scaling parameters of individual PMC's in a core. A PMC library has been developed and used to design cores for communications applications. To demonstrate the effectiveness of the proposed methodology, several subsystems used in a channel LDPC decoder were synthesized using this library where the individual PMC's were optimized for minimum delay. The resulting custom-quality layout have areas ranging from 40/spl times/100 /spl mu/m/sup 2/ to 380/spl times/200 /spl mu/m/sup 2/ and delay in the range of 1.6 ns to 10 ns in 0.18 /spl mu/m, 1.8 V CMOS technology.
{"title":"Parameterized macrocells with accurate delay models for core-based designs","authors":"M. Mansour, Mohammad M. Mansour, A. Mehrotra","doi":"10.1109/ISQED.2003.1194752","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194752","url":null,"abstract":"In this paper we propose a new design methodology targeted for core-based designs using parameterized macrocells (PMC's). This methodology provides the flexibility for instance-based cores to be easily customized for application requirements. By using few scaling parameters to characterize a PMC, a macrocell can be instantiated in virtually any size depending on the required performance. Moreover a new first-order macro delay model is proposed which is a function of the scaling parameters of the PMC which enables accurate delay predictions at the subsystem/core level. The proposed delay model is suitable for use by a delay optimizer to determine the optimum scaling parameters of individual PMC's in a core. A PMC library has been developed and used to design cores for communications applications. To demonstrate the effectiveness of the proposed methodology, several subsystems used in a channel LDPC decoder were synthesized using this library where the individual PMC's were optimized for minimum delay. The resulting custom-quality layout have areas ranging from 40/spl times/100 /spl mu/m/sup 2/ to 380/spl times/200 /spl mu/m/sup 2/ and delay in the range of 1.6 ns to 10 ns in 0.18 /spl mu/m, 1.8 V CMOS technology.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"47 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134260773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194762
C. Oh, D. Blaauw, M. Becer, V. Zolotov, R. Panda, A. Dasgupta
With the increase in current densities, electromigration has become a critical concern in high-performance designs. Typically, electromigration has involved the process of time-domain simulation of drivers and interconnect to obtain average, RMS, and peak current values for each wire segment. However, this approach cannot be applied to large problem sizes where hundreds of thousands of nets must be analyzed, each consisting of many thousands of RC elements. In this paper, we propose a static electromigration analysis approach. We show that under conditions that are typically met by VLSI interconnects, the charge transfer through wire segments of a net can be calculated directly by solving a system of linear equations, thereby eliminating the need for time domain simulation. Also, we prove that under these conditions the charge transfer through a wire segment is independent of the shape of the driver current waveform. From the charge transfer through each wire segment, the average current is obtained directly, as well as approximate RMS and peak currents. We account for the different possible switching scenarios that give rise to unidirectional or bi-directional current by separating the charge transfer from the rising and falling transitions, and also propose approaches for modeling multiple simultaneous switching drivers. The results on a number of industrial circuits demonstrate the accuracy and efficiency of the approach.
{"title":"Static electromigration analysis for signal interconnects","authors":"C. Oh, D. Blaauw, M. Becer, V. Zolotov, R. Panda, A. Dasgupta","doi":"10.1109/ISQED.2003.1194762","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194762","url":null,"abstract":"With the increase in current densities, electromigration has become a critical concern in high-performance designs. Typically, electromigration has involved the process of time-domain simulation of drivers and interconnect to obtain average, RMS, and peak current values for each wire segment. However, this approach cannot be applied to large problem sizes where hundreds of thousands of nets must be analyzed, each consisting of many thousands of RC elements. In this paper, we propose a static electromigration analysis approach. We show that under conditions that are typically met by VLSI interconnects, the charge transfer through wire segments of a net can be calculated directly by solving a system of linear equations, thereby eliminating the need for time domain simulation. Also, we prove that under these conditions the charge transfer through a wire segment is independent of the shape of the driver current waveform. From the charge transfer through each wire segment, the average current is obtained directly, as well as approximate RMS and peak currents. We account for the different possible switching scenarios that give rise to unidirectional or bi-directional current by separating the charge transfer from the rising and falling transitions, and also propose approaches for modeling multiple simultaneous switching drivers. The results on a number of industrial circuits demonstrate the accuracy and efficiency of the approach.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134437051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194765
Takashi Sato, H. Masuda
A newly devised inductance-oscillator (iOSC) has been developed which evaluates inductance impact on on-chip interconnect delay. iOSC is a ring oscillator which is comprised of a set of wires each with different loop inductance and accurate on-chip counter. The equivalent distance to the nearest ground grid, which serves as the current return path, is varied to control wire inductance. A test chip using 0.13 /spl mu/m node process is fabricated to demonstrate the concept of the iOSC. Four interconnect structures are implemented as imperfect coplanar waveguide, imitating clock lines or high-frequency inter-module signal lines. The structure with largest inductance variation measured 99 ps while a twisted ground structure which has small inductance variation measured 6 ps both for 3-mm wires. The experiments confirm that the inductance impact on delay has to be adequately analyzed and controlled to estimate a timing of budget in high-speed LSI designs.
{"title":"Design and measurement of an inductance-oscillator for analyzing inductance impact on on-chip interconnect delay","authors":"Takashi Sato, H. Masuda","doi":"10.1109/ISQED.2003.1194765","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194765","url":null,"abstract":"A newly devised inductance-oscillator (iOSC) has been developed which evaluates inductance impact on on-chip interconnect delay. iOSC is a ring oscillator which is comprised of a set of wires each with different loop inductance and accurate on-chip counter. The equivalent distance to the nearest ground grid, which serves as the current return path, is varied to control wire inductance. A test chip using 0.13 /spl mu/m node process is fabricated to demonstrate the concept of the iOSC. Four interconnect structures are implemented as imperfect coplanar waveguide, imitating clock lines or high-frequency inter-module signal lines. The structure with largest inductance variation measured 99 ps while a twisted ground structure which has small inductance variation measured 6 ps both for 3-mm wires. The experiments confirm that the inductance impact on delay has to be adequately analyzed and controlled to estimate a timing of budget in high-speed LSI designs.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134444062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-03-24DOI: 10.1109/ISQED.2003.1194729
Tom Chen, A. Hajjar
With continuing scaling of CMOS process, process variations in the form of die-to-die and within-die variations become significant which cause timing uncertainty. This paper proposes a method of analytically analyzing statistical behavior of multiple coupled interconnects with an uncertain signal arrival time at each interconnect input (aggressors and the victim). The method utilizes delay change characteristics due to changes in relative arrival time between an aggressor and the victim. The results show that the proposed method is able to accurately predict delay variations through a coupled interconnect.
{"title":"Analyzing statistical timing behavior of coupled interconnects using quadratic delay change characteristics","authors":"Tom Chen, A. Hajjar","doi":"10.1109/ISQED.2003.1194729","DOIUrl":"https://doi.org/10.1109/ISQED.2003.1194729","url":null,"abstract":"With continuing scaling of CMOS process, process variations in the form of die-to-die and within-die variations become significant which cause timing uncertainty. This paper proposes a method of analytically analyzing statistical behavior of multiple coupled interconnects with an uncertain signal arrival time at each interconnect input (aggressors and the victim). The method utilizes delay change characteristics due to changes in relative arrival time between an aggressor and the victim. The results show that the proposed method is able to accurately predict delay variations through a coupled interconnect.","PeriodicalId":448890,"journal":{"name":"Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133882902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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