All-digital Multi-phase Delay Locked Loop For Internal Timing Generation In Embedded And/or High-speed DRAMs

Abstract

We propose an all-digital, multi-phase delay locked loop (DLL) for internal timing generation in embedded DRAMs. The timing generation is achieved by combining the DLL with a command decoder and a resister controlled multi-phase clock counter. The DLL has four phase (d2 step) and six phase (n/3 step) output mode, and employs coarse and fine delay lines to minimize the delay line area while keeping the skew resolution down to a value obtainable by all-digital delay elements. Our DLL operates over a clock range of 125 to 400 MHz with skew adjustment error of*60 ps.