Pub Date : 1997-06-12DOI: 10.1109/VLSIC.1997.623774
Nakatsuka
The specification of the current DVD is reviewed from the view point of the semiconductor technology. LSI technology to realize signal processing and decoding/encoding as well as the laser diode requirement are described. The next generation DVD with the capacity of 15Gbytes per one side of the disc is discussed The impact of DVD to the world of multimedia is also discussed focusing on the home applications such as information home server.
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Pub Date : 1997-06-12DOI: 10.1109/VLSIC.1997.623778
Hector Sanchez, R. Philip, J. Alvarez, G. Gerosa
Hector Sanchez, Ross Philip, Jose Alvarez, Gianfranco Gerosa Motorola Austin. Texas Abstract A 5-bit 2.5V temperature sensor implemented in a 0.35pm CMOS technology is described. The sensor is fully differential and based on the PTAT voltage difference between 2 diodes, yet it does not require a bandga reference. The resolution is 4OC for a temperature range of 0 C to 128OC. The offset error is 12OC over the process corners. The integral nonlinearity is below 1 LSB and the differential nonlinearity is less than 1/2 LSB. The total area of the sensor is 0.192 mm2 and the maximum power dissipation is 1OmW at 2.5V. Introduction The advent of high performance portable electronics puts increased pressure in system integrated solutions. Cost constraints, space limitations, and limited power budgets dictate the need for reducing the number of elements at the board level. External temperature sensors suffer a time-delay in the temperature reading due to the thermal constant from the integrated circuit junction to the external sensor. Furthermore, knowledge of the power consumed and the thermal resistivities is necessary to accurately determine the internal junction temperature. Integrating the temperature sensor results in a lower cost solution that minimizes board area penalty and provides more timely information to enable active thermal management. As a result, operating systems can throttle the processor or invoke a static power savings mode. [ 11
Hector Sanchez, Ross Philip, Jose Alvarez, Gianfranco Gerosa摩托罗拉奥斯汀。摘要介绍了一种采用0.35pm CMOS技术实现的5位2.5V温度传感器。该传感器是完全差分的，基于两个二极管之间的PTAT电压差，但它不需要参考带宽。分辨率为4OC，温度范围为0℃~ 128℃。偏移误差为12OC的过程角。积分非线性小于1 LSB，微分非线性小于1/ 2lsb。传感器总面积为0.192 mm2, 2.5V电压下最大功耗为1OmW。高性能便携式电子产品的出现给系统集成解决方案带来了越来越大的压力。成本限制、空间限制和有限的功率预算决定了需要减少板级元件的数量。由于从集成电路结到外部传感器的热常数，外部温度传感器在温度读数中遭受时间延迟。此外，功耗和热阻的知识是必要的，以准确地确定内部结温度。集成温度传感器可降低解决方案的成本，最大限度地减少电路板面积损失，并提供更及时的信息，以实现主动热管理。因此，操作系统可以限制处理器或调用静态省电模式。[11
{"title":"A CMOS Temperature Sensor For PowerPC RISC Microprocessors","authors":"Hector Sanchez, R. Philip, J. Alvarez, G. Gerosa","doi":"10.1109/VLSIC.1997.623778","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623778","url":null,"abstract":"Hector Sanchez, Ross Philip, Jose Alvarez, Gianfranco Gerosa Motorola Austin. Texas Abstract A 5-bit 2.5V temperature sensor implemented in a 0.35pm CMOS technology is described. The sensor is fully differential and based on the PTAT voltage difference between 2 diodes, yet it does not require a bandga reference. The resolution is 4OC for a temperature range of 0 C to 128OC. The offset error is 12OC over the process corners. The integral nonlinearity is below 1 LSB and the differential nonlinearity is less than 1/2 LSB. The total area of the sensor is 0.192 mm2 and the maximum power dissipation is 1OmW at 2.5V. Introduction The advent of high performance portable electronics puts increased pressure in system integrated solutions. Cost constraints, space limitations, and limited power budgets dictate the need for reducing the number of elements at the board level. External temperature sensors suffer a time-delay in the temperature reading due to the thermal constant from the integrated circuit junction to the external sensor. Furthermore, knowledge of the power consumed and the thermal resistivities is necessary to accurately determine the internal junction temperature. Integrating the temperature sensor results in a lower cost solution that minimizes board area penalty and provides more timely information to enable active thermal management. As a result, operating systems can throttle the processor or invoke a static power savings mode. [ 11","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127407036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-12DOI: 10.1109/VLSIC.1997.623802
Ishida
The demanding constraints of achieving mobilit,y in terms of size, weight, and power without compromising performance and functionality make technologies for mobile computers far more challenging than those for t,heir commodity desktop counterparts. The current success of mobile computers in the market is the result, of differentiation through countless technology innovations in components and subsystems as well as system-level integration, driven by visionary leadership in the field of mobile computing.
{"title":"Technology Innovations In Mobile Computers","authors":"Ishida","doi":"10.1109/VLSIC.1997.623802","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623802","url":null,"abstract":"The demanding constraints of achieving mobilit,y in terms of size, weight, and power without compromising performance and functionality make technologies for mobile computers far more challenging than those for t,heir commodity desktop counterparts. The current success of mobile computers in the market is the result, of differentiation through countless technology innovations in components and subsystems as well as system-level integration, driven by visionary leadership in the field of mobile computing.","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115547495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-12DOI: 10.1109/VLSIC.1997.623775
Moll
The first years have been somewhat controversial as to who invented the transistor. There seems to be no convergence in the disagreement as to whether Shockley or Bardeen was most responsible for the discovery of the "transistor effect." Anything that I might say would not change any existing beliefs. I will give a more complete account of the next five or more years which accounted for much of the technology for the integrated circuit, and which has been largely disregarded in histories of the integrated circuit. The time from 1947 until 1952 was used to study the basic Physical behavior of germanium and silicon.
{"title":"Fifty Years Of The Transistor : The Beginning Of Silicon Technology","authors":"Moll","doi":"10.1109/VLSIC.1997.623775","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623775","url":null,"abstract":"The first years have been somewhat controversial as to who invented the transistor. There seems to be no convergence in the disagreement as to whether Shockley or Bardeen was most responsible for the discovery of the \"transistor effect.\" Anything that I might say would not change any existing beliefs. I will give a more complete account of the next five or more years which accounted for much of the technology for the integrated circuit, and which has been largely disregarded in histories of the integrated circuit. The time from 1947 until 1952 was used to study the basic Physical behavior of germanium and silicon.","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114985195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Introduction As gate oxide thickness is reduced in advanced low-voltage CMOS technologies, protecting the Ti0 circuits’ dielectrics from over-voltage conditions becomes necessary when interfacing to higher voltage buses [1]. 3.3V LVTTL compatible I/O circuits fabricated in a 2.5V CMOS technology are presented. Dynamic dielectric protection techniques are employed to prevent overstressing gate oxide in U 0 circuits of a 4Mb SRAM where undershootlovershoot peaks of -lVi 4.3V can occur before diode clamping begins [2].
{"title":"Dynamic Dielectric Protection For I/0 Circuits Fabricated In A 2.5V CMOS Technology Interfacing To A 3.3V LVTTL Bus","authors":"Connor, Evans, Braceras, Sousa, Abadeer, Hall, Robillard","doi":"10.1109/VLSIC.1997.623836","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623836","url":null,"abstract":"Introduction As gate oxide thickness is reduced in advanced low-voltage CMOS technologies, protecting the Ti0 circuits’ dielectrics from over-voltage conditions becomes necessary when interfacing to higher voltage buses [1]. 3.3V LVTTL compatible I/O circuits fabricated in a 2.5V CMOS technology are presented. Dynamic dielectric protection techniques are employed to prevent overstressing gate oxide in U 0 circuits of a 4Mb SRAM where undershootlovershoot peaks of -lVi 4.3V can occur before diode clamping begins [2].","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123963810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-12DOI: 10.1109/VLSIC.1997.623790
Nagata, Iwata
{"title":"A Macroscopic Substrate Noise Model For Full Chip Mixed-signal Design Verification","authors":"Nagata, Iwata","doi":"10.1109/VLSIC.1997.623790","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623790","url":null,"abstract":"","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132972424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-12DOI: 10.1109/VLSIC.1997.623792
Henkels, Joshi
The advent of superscalar architectures for microprocessors has created the need for register files having many ports. Such multi-porting is at odds with the universal goals of high-density, high-performanc,e, and %e of testing. High-density multi-porting favors single-ended reading and wnting. However, single-ended operation makes high-performance more difficult to achieve. Another issue in VLSI is how to test the numerous embedded arrays. Typically, large memory arrays employ ABIST circuiuy. However, for small arrays, such as register files, the overhead of ABIST is more significant for performance and area, and thus is less acceptable. With this background we have set out to design a 2-write/6-read-port 32 x 64-bit register file which is dense AND fast AND readily testable in a 2.5-V 0.5-pm CMOS technology. Our approach employs self-resetting CMOS (SRCMOS) dynamic circuits [I]. Special attention has been paid toward insuring design robustness with regard to input pulsewidth variations. The testing issue has been dealt with up-front by making the memory cells totally LSSD compatible. Also designed was a dynamic-to-static latch which can be employed to make the register file compatible with either a dynamic or static dataflow.
微处理器的超标量体系结构的出现产生了对具有许多端口的寄存器文件的需求。这种多移植与高密度、高性能、e和%e测试的普遍目标是不一致的。高密度多端口有利于单端读取和输出。然而，单端运算使得高性能更难实现。VLSI的另一个问题是如何测试众多的嵌入式阵列。通常，大型存储器阵列采用ABIST电路。但是，对于较小的数组，例如寄存器文件，ABIST的开销对性能和面积的影响更大，因此不太可接受。在此背景下，我们开始设计一个2写/6读端口32 x 64位寄存器文件，该文件紧凑，快速且易于在2.5 v 0.5 pm CMOS技术中进行测试。我们的方法采用自复位CMOS (SRCMOS)动态电路[1]。在输入脉冲宽度变化的情况下，特别注意确保设计的鲁棒性。测试问题已经通过使内存单元完全兼容LSSD预先处理。还设计了一个动态到静态的锁存器，它可以使寄存器文件与动态或静态数据流兼容。
{"title":"A 500 MHz 32-word X 64-bit 8-port Self-resetting CMOS Register File And Associated Dynamic-to-static Latch","authors":"Henkels, Joshi","doi":"10.1109/VLSIC.1997.623792","DOIUrl":"https://doi.org/10.1109/VLSIC.1997.623792","url":null,"abstract":"The advent of superscalar architectures for microprocessors has created the need for register files having many ports. Such multi-porting is at odds with the universal goals of high-density, high-performanc,e, and %e of testing. High-density multi-porting favors single-ended reading and wnting. However, single-ended operation makes high-performance more difficult to achieve. Another issue in VLSI is how to test the numerous embedded arrays. Typically, large memory arrays employ ABIST circuiuy. However, for small arrays, such as register files, the overhead of ABIST is more significant for performance and area, and thus is less acceptable. With this background we have set out to design a 2-write/6-read-port 32 x 64-bit register file which is dense AND fast AND readily testable in a 2.5-V 0.5-pm CMOS technology. Our approach employs self-resetting CMOS (SRCMOS) dynamic circuits [I]. Special attention has been paid toward insuring design robustness with regard to input pulsewidth variations. The testing issue has been dealt with up-front by making the memory cells totally LSSD compatible. Also designed was a dynamic-to-static latch which can be employed to make the register file compatible with either a dynamic or static dataflow.","PeriodicalId":175678,"journal":{"name":"Symposium 1997 on VLSI Circuits","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130922576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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