Exploration of a Low-power CMOS Voltage Squarer

Abstract

This paper addresses a reported voltage multiplier and explores its use as a voltage squarer with the aim of reducing the power consumption and area. The proposed circuit can operate with a maximum gain of -30.4 up 250kHz. These ones have also shown the total power consumption is about 501 nW at VDD= 1.8 V. In order to reduce the squarer sensitivity to process variations over corners, a bias circuit also sensitive to these variations was used to mitigate such effects. This was verified by pre- and post-layout simulations using transistor's models of standard 0.18 µ m CMOS process.