A Study of CMOS Latch-up by Laser Scanning and Voltage Contrast Techniques

Abstract

The susceptibility of CMOS devices to latch-up becomes of greater concern as the spacing between geometries is reduced. An advanced 1 micron CMOS device is used to examine various methods of determining where on the device latch-up might occur. Two of these methods are laser induced latch-up and scanning electron microscope (SEM) microprobe. A correlation is shown between the two methods.