An integrated low power transceiver system

Abstract

Wireless sensor networks(WSN) demand low power and low cost transceiver design. In this paper, an integrated transceiver system has been designed and fabricated using a 0.13µm CMOS process for ultra low power WSN applications. The system integrates an OOK receiver, a transmitter, RF/DC switches and a voltage regulator which provides comprehensive on-chip biasing circuitry in a 2×2mm2 chip. A common source low noise amplifier (LNA) works at sub-threshold range to achieve maximum power efficiency. A Villard voltage doubler circuit and a voltage transformer have been used to significantly improve the OOK signal demodulation efficiency and the system sensitivity with near zero power consumption. The system obtains a receiver sensitivity of −60 dBm with 4mW@1.4V.