Analyzing Transient Faults and Functional Error Rates of a RISC-V Core: A Case Study

Abstract

It is essential to perform extensive RTL functional fault simulation for critical systems in order to analyze the vulnerability and design error-tolerant measures accordingly. Since the number of faults would be exceedingly large for a full simulation, fault sampling techniques are applied. However, little information are available for fault characteristics, so the sampling might not be effective: often producing no error output or similar output syndromes.In this paper, we utilized an advanced Architecturally Correct Execution (ACE) analysis to study the functional fault characteristics of registers on a RISC-V core. From the results for all registers, only less than 0.34% to 2.76% of total faults need to be simulated. We then further sample and simulate these remained faults at RTL to analyze the categories for failure output syndromes. We found that faults at non-architecture registers have much higher masked results (as high as 90%), as compared with architecture registers (16% – 40%). Therefore, it is suggested that fault sampling should consider register and fault characteristics for a more effective result.