Verification strategy of the CATHEDRAL-I silicon compiler based on the SFG-tracing methodology

Abstract

The application strategy is described of a new verification methodology on the CATHEDRAL-I silicon compiler. The basic goal is to prove the feasibility of an automated verification process based on the presented SFG-tracing concept. This methodology permits the overall evaluation of the lower-level implementation versus the high-level behavioral signal flow graph. Gradually, correspondences between specific signals, called references signals, at the different design levels are mapped during the architecture synthesis. Efficient behavior comparison can be started as soon as those relationships are traced accurately and completely. This task was handled with the aid of the compiled-code symbolic simulator COSMOS.<>