Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218498
U. Hubner, H. Vierhaus
Descriptions are given of the most significant types of defects and their implication on delay effects and overcurrents for different classes of CMOS circuits. Delay fault testing and built-in current testing have emerged as the most promising methods in CMOS testing for high fault coverage. Based on different types of transistor circuits, an analysis is performed to investigate the fault coverage potential of both methods for transistor faults and bridging faults.<>
{"title":"Built-in current testing versus delay fault testing-a case study","authors":"U. Hubner, H. Vierhaus","doi":"10.1109/CMPEUR.1992.218498","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218498","url":null,"abstract":"Descriptions are given of the most significant types of defects and their implication on delay effects and overcurrents for different classes of CMOS circuits. Delay fault testing and built-in current testing have emerged as the most promising methods in CMOS testing for high fault coverage. Based on different types of transistor circuits, an analysis is performed to investigate the fault coverage potential of both methods for transistor faults and bridging faults.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124374736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218431
L. Kotulski, W. Moczurad, J. Jurek
A method for constructing large distributed software systems in an object-oriented way is presented. The authors define a group which is an object in the sense of programming in the large. A group may be distributed over many computing nodes. The concept uses a graph formalism to describe the whole system and its transformations.<>
{"title":"Object-oriented programming in the large using group concept","authors":"L. Kotulski, W. Moczurad, J. Jurek","doi":"10.1109/CMPEUR.1992.218431","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218431","url":null,"abstract":"A method for constructing large distributed software systems in an object-oriented way is presented. The authors define a group which is an object in the sense of programming in the large. A group may be distributed over many computing nodes. The concept uses a graph formalism to describe the whole system and its transformations.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116969429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218419
H. Reichl, G. Fotheringham
Concepts of multi-chip modules (MCMs) are discussed and simulation methods for their design are presented. The basic requirements for MCM materials and interconnection technologies are outlined. Signal transmission behavior and thermal problems are considered. A short survey of technologies for multilayers is given.<>
{"title":"Simulation methods and technologies for multichip modules","authors":"H. Reichl, G. Fotheringham","doi":"10.1109/CMPEUR.1992.218419","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218419","url":null,"abstract":"Concepts of multi-chip modules (MCMs) are discussed and simulation methods for their design are presented. The basic requirements for MCM materials and interconnection technologies are outlined. Signal transmission behavior and thermal problems are considered. A short survey of technologies for multilayers is given.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125787379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218445
J. Herrmann, M. Witthaut
The learning design assistant LEDA provides an environment for the creation of structural register-transfer descriptions. LEDA's inputs constitute an algorithmic behavioral hardware description and a specification of the design goals. The designer uses LEDA as an extended design editor and selects a sequence of allocation operators called the design plan that create register-transfer components for a statement of the algorithm. LEDA's learning component creates from each plan a specific production rule which is generalized by use of an inductive learning mechanism that is tailored to the acquisition of design plans. Each time a rule matches on the selected statement LEDA proposes the execution of the corresponding design plan. In this way LEDA works as an apprentice system, adapts to the design style of the user, and supports the synthesis of the repeatedly occurring parts of algorithm descriptions.<>
{"title":"LEDA-a learning apprentice system that acquires design plans for high-level synthesis of integrated circuits","authors":"J. Herrmann, M. Witthaut","doi":"10.1109/CMPEUR.1992.218445","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218445","url":null,"abstract":"The learning design assistant LEDA provides an environment for the creation of structural register-transfer descriptions. LEDA's inputs constitute an algorithmic behavioral hardware description and a specification of the design goals. The designer uses LEDA as an extended design editor and selects a sequence of allocation operators called the design plan that create register-transfer components for a statement of the algorithm. LEDA's learning component creates from each plan a specific production rule which is generalized by use of an inductive learning mechanism that is tailored to the acquisition of design plans. Each time a rule matches on the selected statement LEDA proposes the execution of the corresponding design plan. In this way LEDA works as an apprentice system, adapts to the design style of the user, and supports the synthesis of the repeatedly occurring parts of algorithm descriptions.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126070622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218448
A. Seif
The development of adaptive pattern recognition control was based on the analysis and description of cognition and thinking of a human control engineer, particularly its associative and qualitative nature. This analysis yielded a design procedure that can be divided into two basic tasks which can be treated separately: pattern description (Task 1) and assignment of control action to patterns. (Task 2). The adaptive pattern recognition controller (APRC) scheme uses an elementary pattern set approach for pattern description (Task 1) and an iterative adaptive controller adjustment strategy for a PI controller setting (Task 2). The parameter-adaptive PI controller based on this elementary pattern approach is described. It yielded good results in simulation studies for linear time-varying stable minimum/nonminimum phase processes with dead time. The application to two laboratory plants for the control of flow, pressure, and temperature was successful.<>
{"title":"On the adaptive pattern recognition control","authors":"A. Seif","doi":"10.1109/CMPEUR.1992.218448","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218448","url":null,"abstract":"The development of adaptive pattern recognition control was based on the analysis and description of cognition and thinking of a human control engineer, particularly its associative and qualitative nature. This analysis yielded a design procedure that can be divided into two basic tasks which can be treated separately: pattern description (Task 1) and assignment of control action to patterns. (Task 2). The adaptive pattern recognition controller (APRC) scheme uses an elementary pattern set approach for pattern description (Task 1) and an iterative adaptive controller adjustment strategy for a PI controller setting (Task 2). The parameter-adaptive PI controller based on this elementary pattern approach is described. It yielded good results in simulation studies for linear time-varying stable minimum/nonminimum phase processes with dead time. The application to two laboratory plants for the control of flow, pressure, and temperature was successful.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123033830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218492
E. Zehendner, T. Ungerer
A data flow architecture is presented that utilizes several levels of parallelism by a three-level hierarchical hardware structure. Task level parallelism was exploited by the architectural structure of a distributed memory multiprocessor and a load distribution strategy that supports parallel execution of procedure activations. Block and instruction level parallelism was utilized by token-passing, similar to large-grain data flow. Subinstruction level parallelism was exploited by single instruction, multiple data (SIMD) evaluation of complex machine instructions.<>
{"title":"A large-grain data flow architecture utilizing multiple levels of parallelism","authors":"E. Zehendner, T. Ungerer","doi":"10.1109/CMPEUR.1992.218492","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218492","url":null,"abstract":"A data flow architecture is presented that utilizes several levels of parallelism by a three-level hierarchical hardware structure. Task level parallelism was exploited by the architectural structure of a distributed memory multiprocessor and a load distribution strategy that supports parallel execution of procedure activations. Block and instruction level parallelism was utilized by token-passing, similar to large-grain data flow. Subinstruction level parallelism was exploited by single instruction, multiple data (SIMD) evaluation of complex machine instructions.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121278320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218528
C. Fan, G. Hommel
Generalized stochastic Petri nets were used to model time-constrained message transmission over a single multiple-access channel to get the performance limits, which show the percentage of successful message transmission. These Petri net models reflect different assumptions about the laxity and length distributions of real-time messages. The results from the Petri net models are shown to agree with those from queuing system models.<>
{"title":"Modeling time-constrained multiple-access message transmission by generalized stochastic Petri nets","authors":"C. Fan, G. Hommel","doi":"10.1109/CMPEUR.1992.218528","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218528","url":null,"abstract":"Generalized stochastic Petri nets were used to model time-constrained message transmission over a single multiple-access channel to get the performance limits, which show the percentage of successful message transmission. These Petri net models reflect different assumptions about the laxity and length distributions of real-time messages. The results from the Petri net models are shown to agree with those from queuing system models.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116344976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218399
S. Manoharan
Genesis is a library of C++ classes that serves as building blocks in modeling parallel architectures. This paper presents the architectural representation scheme on which Genesis is based. The design choices of Genesis and some of the reasons behind the choices are discussed. The author describes the way the performance parameters (architecture, program, assignment method, and routing scheme) are specified in Genesis. Some of the implementation details are considered. Some related simulation systems are reviewed and compared with Genesis.<>
{"title":"Genesis: a generic simulation subsystem for parallel architectures","authors":"S. Manoharan","doi":"10.1109/CMPEUR.1992.218399","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218399","url":null,"abstract":"Genesis is a library of C++ classes that serves as building blocks in modeling parallel architectures. This paper presents the architectural representation scheme on which Genesis is based. The design choices of Genesis and some of the reasons behind the choices are discussed. The author describes the way the performance parameters (architecture, program, assignment method, and routing scheme) are specified in Genesis. Some of the implementation details are considered. Some related simulation systems are reviewed and compared with Genesis.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130433154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218442
J. Nijhuis, S. Neusser, L. Spaanenburg, J. Heller, J. Sponnemann
The authors present a neural and fuzzy solution to the collision avoidance problem of an automated guided vehicle (AGV). They describe the AGV and its sensor characteristics. Two methods based on neural networks and fuzzy logic, respectively, have been developed. The advantages and problems of each approach are evaluated. Experiments showed that the collision avoidance problem can be successfully tackled by both neural networks and fuzzy logic. Both approaches have the advantage that almost no control-specific knowledge is needed. Neural network controllers are easier to design, whereas the operation of the fuzzy logic controller is more understandable, i.e., individual rules can be adjusted to optimize certain parts of the controller behavior.<>
{"title":"Evaluation of fuzzy and neural vehicle control","authors":"J. Nijhuis, S. Neusser, L. Spaanenburg, J. Heller, J. Sponnemann","doi":"10.1109/CMPEUR.1992.218442","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218442","url":null,"abstract":"The authors present a neural and fuzzy solution to the collision avoidance problem of an automated guided vehicle (AGV). They describe the AGV and its sensor characteristics. Two methods based on neural networks and fuzzy logic, respectively, have been developed. The advantages and problems of each approach are evaluated. Experiments showed that the collision avoidance problem can be successfully tackled by both neural networks and fuzzy logic. Both approaches have the advantage that almost no control-specific knowledge is needed. Neural network controllers are easier to design, whereas the operation of the fuzzy logic controller is more understandable, i.e., individual rules can be adjusted to optimize certain parts of the controller behavior.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134406966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218446
K. Milzner, B. Leifhelm
A novel approach to the integration of machine learning into a knowledge-based CAD environment is presented. To achieve increased learning efficiency the learning system combines learning from observation during normal operation of the CAD system with active experimentation during its idle times. Automated example generation is based on metaknowledge about the design expertise implemented in the CAD system. By reusing specific parts of this knowledge to construct experiments the learning system automatically adapts to improvements and extensions in the host system. The current prototype was able to learn analytical knowledge about worst-case estimations for analog circuit blocks.<>
{"title":"Learning by observation and active experimentation in a knowledge based CAD-environment","authors":"K. Milzner, B. Leifhelm","doi":"10.1109/CMPEUR.1992.218446","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218446","url":null,"abstract":"A novel approach to the integration of machine learning into a knowledge-based CAD environment is presented. To achieve increased learning efficiency the learning system combines learning from observation during normal operation of the CAD system with active experimentation during its idle times. Automated example generation is based on metaknowledge about the design expertise implemented in the CAD system. By reusing specific parts of this knowledge to construct experiments the learning system automatically adapts to improvements and extensions in the host system. The current prototype was able to learn analytical knowledge about worst-case estimations for analog circuit blocks.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130848771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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