Anti-resonance peak frequency control by variable on-die capacitance

W. Ichimura, S. Kiyoshige, Masahiro Terasaki, R. Kobayashi, G. Kubo, H. Otsuka, T. Sudo
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引用次数: 2

Abstract

Power integrity design has been becoming important in the advanced CMOS digital systems, because power supply noise induces logic instability and electromagnetic radiation. Especially, anti-resonance peaks in power distribution network (PDN) due to the chip-package interaction induce the unwanted power supply fluctuation, and result in large electromagnetic radiation. In this paper, power supply noises and total impedances of power distribution network (PDN) for the variable structure of on-die capacitances have been examined. In addition, power supply noise and total PDN impedance have been examined by changing the number of power supply terminals. As a result, it has been proved that anti-resonance peaks could be controlled by on-die capacitance and the number of power supply terminals. Simulated anti-resonance peak frequencies were well correlated with the peak frequency spectra of measured power supply noise.
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可变片上电容抗谐振峰值频率控制
由于电源噪声会引起逻辑不稳定和电磁辐射,因此电源完整性设计在先进的CMOS数字系统中变得越来越重要。特别是在配电网中,由于芯片与封装之间的相互作用而产生的抗谐振峰值会引起不必要的电源波动,从而产生较大的电磁辐射。本文研究了可变电容结构下配电网的电源噪声和总阻抗。此外,通过改变电源端子的数量,研究了电源噪声和PDN总阻抗。结果表明,抗谐振峰值可以通过片上电容和电源端子数来控制。模拟的抗谐振峰值频率与实测电源噪声的峰值频谱具有良好的相关性。
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