A comparative performance analysis of CMOS XOR XNOR circuits

Abstract

This work presents the contemplate review of diverse approaches employed to design XOR/XNOR circuits, as these circuits are the nucleus circuit for numerous computational intensive arithmetic circuits in VLSI. This paper describes the comparative analysis of performance evaluation of various reported XOR and XNOR circuits designs. The different designs are compared by performing the transistor level simulations on the benchmark circuit using HSPICE on 90nm PTM CMOS technology and analyzing the results in comprehensive manner. Based on the intensive simulations, the XOR/XNOR designs with feedback transistors outperforms well in comparison to other previously existing circuits in terms of high speed, low power and output voltage without any logic degradation with high noise tolerance capability.