A high speed power efficient dynamic comparator designed in 90nm CMOS technology

Abstract

A fully dynamic latched comparator has been designed to meet the requirement of high speed and low power consumption. Such comparators are used in high speed data converters. In this work, dynamic comparators are designed in two different technologies and compared on the basis of delay, offset voltage and power consumption. These comparators work on the concept of charge sharing. Main focus is given towards reduction of both propagation delay and the power dissipation, which will be beneficial in improving performance of the comparator. 90nm CMOS technology is used to simulate the design with 1 V supply voltage. Hspice is used for designing and functional verification.