{"title":"An Integrated Security System for Bank Lockers Using Gated D-Latch","authors":"Silpakesav Velagaleti","doi":"10.1109/INOCON57975.2023.10101343","DOIUrl":null,"url":null,"abstract":"This paper discusses the design of a Bank locker system. Three different versions of a Bank Locker Security (BLS) System is designed and observed the power consumption at different process corners and different supply voltages. The simulations are measured at 27o C temperature. The power consumption is observed at the supply voltage from 600mV to 1. 2V. The power consumption is less with slow-slow (SS) process corner at 66 MHZ and 200 MHz respectively. This BLS is designed using 45nm CMOS technology.","PeriodicalId":113637,"journal":{"name":"2023 2nd International Conference for Innovation in Technology (INOCON)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 2nd International Conference for Innovation in Technology (INOCON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/INOCON57975.2023.10101343","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper discusses the design of a Bank locker system. Three different versions of a Bank Locker Security (BLS) System is designed and observed the power consumption at different process corners and different supply voltages. The simulations are measured at 27o C temperature. The power consumption is observed at the supply voltage from 600mV to 1. 2V. The power consumption is less with slow-slow (SS) process corner at 66 MHZ and 200 MHz respectively. This BLS is designed using 45nm CMOS technology.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
