{"title":"On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFS","authors":"P. Vivet, E. Beigné, H. Lebreton, N. Zergainoh","doi":"10.1007/978-3-642-17752-1_10","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"57 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Workshop on Power and Timing Modeling, Optimization and Simulation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1007/978-3-642-17752-1_10","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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