G. Furano, A. Tavoularis, Lucana Santos, V. Ferlet-Cavrois, C. Boatella, R. G. Alía, P. Fernandez-Martínez, M. Kastriotou, V. Wyrwoll, S. Danzeca, M. Tali, Dejan Gacnik, I. Kramberger, L. Juul, Konstantinos Maragos, G. Lentaris
{"title":"FPGA SEE Test with Ultra-High Energy Heavy Ions","authors":"G. Furano, A. Tavoularis, Lucana Santos, V. Ferlet-Cavrois, C. Boatella, R. G. Alía, P. Fernandez-Martínez, M. Kastriotou, V. Wyrwoll, S. Danzeca, M. Tali, Dejan Gacnik, I. Kramberger, L. Juul, Konstantinos Maragos, G. Lentaris","doi":"10.1109/DFT.2018.8602958","DOIUrl":null,"url":null,"abstract":"The use of System-on-Chip (SoC) solutions in the design of space-borne data handling systems is an important step towards further miniaturization in space. In cubesats and in many aggressive commercial missions, use of Commercial-Off-The-Shelf (COTS) components is becoming the rule, rather than the exception and many of those are complex SoC, multiprocessor system-on-chip (MPSoC), SiP (System in package) or AMS-SoC (Analog/Mixed Signal SoC). Those changes are triggering attempts to modify the way we approach and conduct radiation tolerance and testing of electronics. Among the changes that have an impact on Single Event Effect (SEE) testing are scaling of geometries, supply voltages, new materials, new packaging technologies, and overall speed and device complexity challenges. In the frame of the ESA-CERN cooperation agreement, certain ESA projects had access to the most intense beam of ultra-high energy heavy ions available at the Super Proton Synchrotron (SPS) particle accelerator. This paper will present challenges and advantages of SEE tests of complex electronic devices in this new environment and its relevance for future space missions.","PeriodicalId":297244,"journal":{"name":"2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFT.2018.8602958","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
The use of System-on-Chip (SoC) solutions in the design of space-borne data handling systems is an important step towards further miniaturization in space. In cubesats and in many aggressive commercial missions, use of Commercial-Off-The-Shelf (COTS) components is becoming the rule, rather than the exception and many of those are complex SoC, multiprocessor system-on-chip (MPSoC), SiP (System in package) or AMS-SoC (Analog/Mixed Signal SoC). Those changes are triggering attempts to modify the way we approach and conduct radiation tolerance and testing of electronics. Among the changes that have an impact on Single Event Effect (SEE) testing are scaling of geometries, supply voltages, new materials, new packaging technologies, and overall speed and device complexity challenges. In the frame of the ESA-CERN cooperation agreement, certain ESA projects had access to the most intense beam of ultra-high energy heavy ions available at the Super Proton Synchrotron (SPS) particle accelerator. This paper will present challenges and advantages of SEE tests of complex electronic devices in this new environment and its relevance for future space missions.