Some limitations to speed-independence in asynchronous circuits

M. Bush, M. B. Josephs
{"title":"Some limitations to speed-independence in asynchronous circuits","authors":"M. Bush, M. B. Josephs","doi":"10.1109/ASYNC.1996.494442","DOIUrl":null,"url":null,"abstract":"Asynchronous circuits are often designed to operate correctly whatever the speeds of the elements (e.g., logic gates) out of which they are constructed. Sometimes, however, one finds that it is not possible to synthesise a speed-independent circuit that implements a given specification. The fundamental reason for these limitations to speed-independence is that certain local properties of elements manifest themselves as global properties of circuits, properties that may be incompatible with the specification to be implemented. This paper investigates several such properties (concerned with persistence, commutativity and inertia) by means of a formal analysis carried out using Josephs' Receptive Process Theory.","PeriodicalId":365358,"journal":{"name":"Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASYNC.1996.494442","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5

Abstract

Asynchronous circuits are often designed to operate correctly whatever the speeds of the elements (e.g., logic gates) out of which they are constructed. Sometimes, however, one finds that it is not possible to synthesise a speed-independent circuit that implements a given specification. The fundamental reason for these limitations to speed-independence is that certain local properties of elements manifest themselves as global properties of circuits, properties that may be incompatible with the specification to be implemented. This paper investigates several such properties (concerned with persistence, commutativity and inertia) by means of a formal analysis carried out using Josephs' Receptive Process Theory.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
异步电路中速度独立性的一些限制
异步电路通常被设计成无论构成它们的元件(如逻辑门)的速度如何,都能正确地工作。然而,有时人们发现不可能合成实现给定规格的与速度无关的电路。这些速度无关性限制的根本原因是元件的某些局部属性表现为电路的全局属性,这些属性可能与要实现的规范不兼容。本文利用约瑟夫的接受过程理论,用形式化分析的方法研究了这类性质(有关持久性、交换性和惯性)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
The AMULET2e cache system Pulse-driven dual-rail logic gate family based on rapid single-flux-quantum (RSFQ) devices for asynchronous circuits Counterflow pipeline based dynamic instruction scheduling Control resynthesis for control-dominated asynchronous designs Complete state encoding based on the theory of regions
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1