H.264/AVC intra prediction encoding chain implementation on MPSoC based on slice level parallelism

Abstract

Multiprocessor System on Chip (MPSoC) is a promising way to reduce the processing time required by digital multimedia encoders such the most complex H.264/Advanced Video Coding. MPSoC contributes in this challenge by offering a high performance computing, little system on chip (SoC) surface, and low power consumption. In order to reduce the execution time of H.264/AVC intra only encoding chain, an efficient parallel processing on MPSoC architecture is proposed in this paper. The proposed parallel processing is based on a mixed partitioning which combines slice and macro blocks line level parallelism. The proposed architecture is designed through SoCLib platform. For performances evaluation, three MIPS32 processors are used to accelerate the encoding time. Experimental results for High Definition (HD) video sequences show that the proposed implementation allows a saving of 65.7% in processing time compared to a single CPU execution. Furthermore, the proposed solution is characterized by a relatively low memory size which positively affects the final circuit surface.