Phase shift lithography in the manufacture of sub-120 nm low-voltage DSP circuits

Abstract

In this paper the successful integration of alternating aperture phase-shift lithography methodology into a 0.12 /spl mu/m random-logic CMOS process flow is discussed. This methodology enabled the fabrication of a digital signal processor (DSP) operating at 100 MHz with a 1.0 V supply voltage with a measured stand-by current of less than 100 /spl mu/A and a dynamic power dissipation of 0.23 mW/MHz. The phase-shifted DSP chip clocks above 170 MHz at 1.5 V, a threefold improvement over the 0.24 /spl mu/m device, demonstrating an improvement approximately proportional to 1/L/sup 2/. A commercially available software tool was used to generate the phase-shift mask patterns to reach this milestone DSP performance. Two million transistors in this DSP integrated circuit with critical dimensions (CD) of 0.24 /spl mu/m are phase shifted down to gate lengths below 0.12 /spl mu/m. The CMOS process flow is optimized to achieve a low power-delay product and transistor implants are designed for conventionally designed circuits to be operational at low voltages. The technology features symmetric NMOS/PMOS threshold-voltage, nitrogen incorporated gate oxides, and a novel WSi/WSiN-polycide gate electrode stack to prevent Boron lateral diffusion.