A 180 nm Low-Cost Operational Amplifier for IoT Applications

Abstract

This paper presents the design and post-layout simulation of a two-stage operational amplifier (opamp) with Miller compensation, using a third stage that acts as output buffer to drive large loads. The TSMC 0.18μm PDK was used for the design, simulation and implementation in Cadence Virtuoso. The opamp exhibits 20μW power consumption with a 1-V rail-to-rail supply. Post layout simulation shows a unity gain bandwidth (UGBW) of 69.18 MHz $(A_{v}=\mathbf{49.63dB})$ with a phase margin (PM) larger than 86° and a Slew rate of $19.87\mu\mathrm{V}_\mathrm{s}$; making our design suitable for small and large signal applications.