Codesign system performance based on memory configurations

Abstract

In the codesign methodology, the system specification is partitioned into hardware and software subsystems. Subsequently the former is synthesised into custom hardware, while the latter is compiled into processor code. A common target architecture is based on a shared bus uing a single-port global memory. Therefore, the system performance is compromised by bus contention. The hardware and software subsystems communicate through either a busy-wait or an interrupt mechanism. This paper presents two alternatives for memory configuration: one uses a dual-port memory to substitute the original single-port shared memory of the target architecture and the other uses a cache memory for the hardware subsystem, while keeping the single-port shared memory. The dual-port memory configuration aims to avoid to contention, whereas the cache memory configuration aims to reduce bus contention during the hardware subsystem memory accesses. The objective of this study is to achieve an acceptable performance in terms of the overall execution time of an application.