On the Issues of Subnanometer EOT Gate Dielectric Scaling

Abstract

Only with a few generations after the introduction of high-dielectric constant (high-k) gate dielectric for equivalent oxide thickness (EOT) scaling, the scaling rate has lost its momentum already. The EOT of the state-of-the-art technology is in the range of 0.8 to 0.9 nm which is not much thinner than the tunneling silicon oxide used before the adoption of high-k or EOT strategy; it is predicted that the downsizing rate will be around 0.03 nm/generation only. There are some fundamental technological issues limit the subnanometer EOT scaling, not to mention there are lots of characteristic degradation and reliability issues for the adoption of high-k film. In this talk, we shall review the scaling trend and key technological advancements in CMOS gate dielectric scaling. Then the technological limitations due to the interface layers and surface roughness when the EOT approaching atomic scale/roughness scale will be discussed in detail.