Using WAVES for verification of synthesized sub-components in a deeply hierarchical design

Abstract

The Waveform and Vector Exchange Standard (WAVES) and organically developed tools were used in a new testing and verification methodology for an in-house design of a massively parallel graphics accelerator integrated circuit with approximately 700,000 transistors. The purpose of the methodology was to automate as much as possible the functional testing of all implementation levels. WAVES and its associated support tools provide a convenient method to quickly and accurately develop test benches for functional verification in VHDL at all levels. Additional tools were developed in-house to add capabilities for the testing and verification process. These added capabilities made WAVES useful for generating tests for gate and transistor models of the design components.