{"title":"An on-chip automatic tuning circuit with VCO for multi-bit A/D-D/A calibration","authors":"Sung-Dae Lee, Sang-Kyu Kim, W. Lee","doi":"10.1109/APASIC.1999.824087","DOIUrl":null,"url":null,"abstract":"In this paper we introduce an on-chip automatic tuning circuit using a proposed voltage-controlled oscillator. The prepared on-chip automatic tuning circuit is designed in a 0.65 /spl mu/m 3.3 V CMOS process for tuning of the passive component variation. This tuning circuit could reduce the large differences between code values and real output values, however, the dual slope tuning circuit cannot reduce them. Also it also does not generate signal modulation because the tuning codes are fixed in the normal operation The proposed on-chip automatic tuning circuit could increase the accuracy of the passive component and reduce the complexity of the tuning circuit. Since the proposed on-chip automatic tuning circuit operates at several hundreds MHz speed, it can be applied to real time operation especially a calibration circuit for a high speed A/D converter. It may be able to compensate for the variation of passive components within a maximum range of /spl plusmn/1.0% at /spl plusmn/56% RC time constant variation of the detecting integrator.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APASIC.1999.824087","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper we introduce an on-chip automatic tuning circuit using a proposed voltage-controlled oscillator. The prepared on-chip automatic tuning circuit is designed in a 0.65 /spl mu/m 3.3 V CMOS process for tuning of the passive component variation. This tuning circuit could reduce the large differences between code values and real output values, however, the dual slope tuning circuit cannot reduce them. Also it also does not generate signal modulation because the tuning codes are fixed in the normal operation The proposed on-chip automatic tuning circuit could increase the accuracy of the passive component and reduce the complexity of the tuning circuit. Since the proposed on-chip automatic tuning circuit operates at several hundreds MHz speed, it can be applied to real time operation especially a calibration circuit for a high speed A/D converter. It may be able to compensate for the variation of passive components within a maximum range of /spl plusmn/1.0% at /spl plusmn/56% RC time constant variation of the detecting integrator.