A 120nm low power asynchronous ADC

Abstract

This paper discusses the development of a new kind of low power processing chain which dynamically adapts sampling frequency to signals. Thus, the design of an asynchronous analog-to-digital converter (A-ADC) is tackled. Its principle is based on a nonuniform sampling scheme and asynchronous technology that allow significant activity and power savings. A test chip targetting 10-bit speech applications has been fabricated using the 120nm CMOS process from STMicroelectronics. The power consumption is lower than 180/spl mu/W leading to a figure of merit two times better than those of classical Nyquist converters recently published.