Thermal transient characterization methodology for single-chip and stacked structures

Abstract

High-power semiconductor packages typically exhibit a 3D heat flow, resulting in large lateral changes in chip and case surface temperature. For single-chip devices we propose to use an unambiguous definition for the junction-to-case thermal resistance as a key parameter, based on a transient measurement technique with much higher repeatability, also for very low thermal resistances compared to a two-point thermal resistance measurement. The technique is illustrated on thermal transient measurements of power MOSFETs. A comparison between different thermal coupling to the ambient is used to demonstrate the method's capability to reveal even subtle internal details of the package. The concept is extended to multichip and stacked-chip structures, where transfer impedances have to be introduced. Here, the dynamic properties of the package are important and complex impedance mapping is the proper way to characterize the package.