Pattern generation for verification of VHDL behavioral-level design

Abstract

Design methodology has been changing from schematic-based design to HDL based-design. In HDL based-design, coding errors may exist and it takes much time to be found and corrected in design process. Thus an efficient method to verify the correctness of the coding itself is required. In this paper, we proposed a verification method for VHDL behavioral level design. VHDL coding is converted into CDFG and verification patterns are generated. Generated patterns are applied to VHDL design and the gold-unit. If there is difference in responses from VHDL design and gold-unit, coding error exists in VHDL design, and the proposed method detects and locates the coding error. Simulation result showed that the proposed method could verify the correctness of the design efficiently.