{"title":"Analysis of TRL circuit propagation delay","authors":"W. Dunnet, E. P. Auger, A. Scott","doi":"10.1145/1458043.1458066","DOIUrl":null,"url":null,"abstract":"Synopsis: A program to design transistor-resistor logic (TRL) circuits and compile TRL propagation delay tables on a digital computer is presently underway at the Sylvania Data Processing Laboratory. This paper points to the need for such a program and describes transistor and TRL circuit studies that have resulted in the basic relationships being programmed.","PeriodicalId":245493,"journal":{"name":"AIEE-ACM-IRE '58 (Eastern)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1958-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"AIEE-ACM-IRE '58 (Eastern)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1458043.1458066","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
Synopsis: A program to design transistor-resistor logic (TRL) circuits and compile TRL propagation delay tables on a digital computer is presently underway at the Sylvania Data Processing Laboratory. This paper points to the need for such a program and describes transistor and TRL circuit studies that have resulted in the basic relationships being programmed.
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