SystemVerilog Assertion Based Verification of AMBA-AHB

Abstract

Assertion Based Verification (ABV) is one of the widely used verification technique to enhance the verification quality and reduce the debugging time of complex system-on-chip (SOC) designs in order to speedup the verification process. A verification environment to verify an AMBA-AHB (Advanced High Performance Bus) by using SystemVerilog Assertion (SVA) is presented in this paper as it can easily be turned ON or OFF at any instant during simulation as needed. First the AMBA-AHB is modeled using 3 masters and 4 slaves in verilog language. This design is then verified using SVA binding construct in ModelSim. Binding allows verification engineers to add assertions to design without touching the design files. The different properties of AMBA-AHB and its corner cases properties are verified using ModelSim and the total coverage report of the design is calculated. In this paper, we define the assertions in separate modules and use the BIND SystemVerilog feature to bind the assertion modules to the Verilog RTL modules. Here, we have clear separation between the RTL modules and the assertion modules.