An Efficient Self Post Package Repair Algorithm and Implementation in Memory System with on-chip-EGG

Abstract

An efficient self post package repair algorithm using on-chip-ECC is proposed and the circuit implementation details are presented. The proposed algorithm identifies and stores the addresses of hard fault detected by on-chip-ECC during post package test phase and performs subsequent repairs with changing supply voltage level controlled by tester. A yield improvement by 1~1.5% is expected and the efficiency of test and repair steps is enhanced by about 58~67%. The chip size overhead for its implementation is estimated to be under 0.4% for an 80 nm 1 Gb memory.