Design and Implementation of Sixteen-bit Low Power and Area Efficient Dadda Multiplier

Abstract

Low power and area efficient 16-bit multiplier has been designed and implemented using the Dadda algorithm. Here, the prime building block having low power dissipation and area efficient optimized full adder architecture and Carry Look-Ahead (CLA) adder is designed and implemented. Designing full adder is done by making use of complex cells in the technology node of 65nm to reduce the power dissipation and minimum area using TSMC 65nm library. The proposed multiplier design is optimized, simulated using ISE simulator and synthesized using Cadence Genus EDA tool and results are demonstrated. The power and area of the Dadda multiplier designed using proposed full adder is minimum compared to conventional design. The power and area are improved by an amount of 15.32% and 1.91% respectively, than the conventional-full adder. Dadda Multiplier designed here is used to implement 16-bit ALU the power and area obtained are 20.65% and 1.8% lesser than the existing design.