Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016931
Snehal Kapse, S. B. Gundre
In paper, a modified design and response of fractal shape dual-band Electromagnetic bandgap (EBG) integrated textile antenna is detailed. Designed antenna works on the GSM and ISM bands with frequency 1.8 GHz and 2.45 GHz respectively. Antenna prototype is made up of common clothing fabric like jean and adhesive copper tape. The paper contains software simulation on Ansoft HFSS (high-frequency structure simulator) and hardware model of the antenna with EBG and without EBG. Required results are found even after changes in the structure of EBG. The design of monopole antenna, bandgap structure and their integrated is presented. The $3 times 3$ bandgap array structure is used to reduces the back radiation into human body over 16 dB.
{"title":"Fractal Shape Dual-Band EBG integrated Textile Antenna","authors":"Snehal Kapse, S. B. Gundre","doi":"10.1109/RTEICT46194.2019.9016931","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016931","url":null,"abstract":"In paper, a modified design and response of fractal shape dual-band Electromagnetic bandgap (EBG) integrated textile antenna is detailed. Designed antenna works on the GSM and ISM bands with frequency 1.8 GHz and 2.45 GHz respectively. Antenna prototype is made up of common clothing fabric like jean and adhesive copper tape. The paper contains software simulation on Ansoft HFSS (high-frequency structure simulator) and hardware model of the antenna with EBG and without EBG. Required results are found even after changes in the structure of EBG. The design of monopole antenna, bandgap structure and their integrated is presented. The $3 times 3$ bandgap array structure is used to reduces the back radiation into human body over 16 dB.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116755224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016877
Samruddhi Chavan, Vivek Rathi, Namrata Birnale
Distillation column is an integral process component where better control means minor compromise in the quality leading to lower energy consumption, which is difficult to achieve in a non linear MIMO system. The traditional PID technique finds difficulty in achieving the setpoint for this nonlinear system with substantial time delays. The objective of this paper is to present a more robust approach of fuzzy logic control for such complex systems, where FLC is designed and then combined with PID using MATLAB and the system responses are compared in the simulation environment. This control algorithm delivers a stable transient and dynamic response for the desired products.
{"title":"Implementation of fuzzy logic control for FOPDT model of distillation column","authors":"Samruddhi Chavan, Vivek Rathi, Namrata Birnale","doi":"10.1109/RTEICT46194.2019.9016877","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016877","url":null,"abstract":"Distillation column is an integral process component where better control means minor compromise in the quality leading to lower energy consumption, which is difficult to achieve in a non linear MIMO system. The traditional PID technique finds difficulty in achieving the setpoint for this nonlinear system with substantial time delays. The objective of this paper is to present a more robust approach of fuzzy logic control for such complex systems, where FLC is designed and then combined with PID using MATLAB and the system responses are compared in the simulation environment. This control algorithm delivers a stable transient and dynamic response for the desired products.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125880091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016965
M. Chandrashekara, S. Rohith
This paper mainly describes the design of 8-bit Vedic multiplier and its performance comparison with existing multiplier such as i) Booth multiplier ii) Array multiplier iii) Wallace tree multiplier. Vedic calculations are the olden scheme of mathematics, which has a procedure of mathematical calculations to compute the multiplication of two 8-bit number. In this work Urdhva Tiryagbhyam (vertical and crosswise) Vedic sutra is used for multiplier design which provides better performance and consumes lesser time for computation. The Urdhva Tiryagbhyam is the finest sutra and universal one among additional sutras and which represents the different multiplication process compared to normal multiplication. In this work, Modified Carry Save Adder (MCSA) is used to compute the sum of partially generated products. It reduces the computational delay towards the addition of unfinished products. The proposed design uses the Verilog HDL to develop the algorithm. The XILINX 14.7 software tool is used to simulate and synthesize the code. The proposed design is also verified on Spartan-6 Field Programmable Gate Array (FPAGA). Finally, the proposed 8-bit multiplier design is compared with 8-bit Booth multiplier, Array multiplier and Wallace tree multiplier in terms of Area, Memory and Delay. The result shows proposed 8-bit Vedic multiplier is efficient and consumes 14.219ns time for the multiplication process which is better compared to 8-bit, Booth multiplier, Array multiplier and Wallace tree multiplier.
{"title":"Design of 8 Bit Vedic Multiplier Using Urdhva Tiryagbhyam Sutra With Modified Carry Save Adder","authors":"M. Chandrashekara, S. Rohith","doi":"10.1109/RTEICT46194.2019.9016965","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016965","url":null,"abstract":"This paper mainly describes the design of 8-bit Vedic multiplier and its performance comparison with existing multiplier such as i) Booth multiplier ii) Array multiplier iii) Wallace tree multiplier. Vedic calculations are the olden scheme of mathematics, which has a procedure of mathematical calculations to compute the multiplication of two 8-bit number. In this work Urdhva Tiryagbhyam (vertical and crosswise) Vedic sutra is used for multiplier design which provides better performance and consumes lesser time for computation. The Urdhva Tiryagbhyam is the finest sutra and universal one among additional sutras and which represents the different multiplication process compared to normal multiplication. In this work, Modified Carry Save Adder (MCSA) is used to compute the sum of partially generated products. It reduces the computational delay towards the addition of unfinished products. The proposed design uses the Verilog HDL to develop the algorithm. The XILINX 14.7 software tool is used to simulate and synthesize the code. The proposed design is also verified on Spartan-6 Field Programmable Gate Array (FPAGA). Finally, the proposed 8-bit multiplier design is compared with 8-bit Booth multiplier, Array multiplier and Wallace tree multiplier in terms of Area, Memory and Delay. The result shows proposed 8-bit Vedic multiplier is efficient and consumes 14.219ns time for the multiplication process which is better compared to 8-bit, Booth multiplier, Array multiplier and Wallace tree multiplier.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125403916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016893
G. Walunjkar, A. Koteswara Rao
Peoples trapped in the disastrous areas may have chances to survive if they are rescued in seventy two hours. Ad hoc networks are considered more suitable for such scenarios due to infrastructure-less feature. Two different mobility models - Reference group Mobility Model and Disaster Area Model are generally used in such scenario. In this paper, various ad hoc routing protocols such as destination distance vector routing protocol, dynamic source routing protocol, ad hoc on demand routing protocol and ad hoc on demand multipath routing protocol are discussed and analyzed using reference group mobility models and disaster area model. Also these protocols are compared using various performance metrics such as packet delivery ratio, delay, throughput, control overhead, average energy consumed etc.
{"title":"Simulation and Evaluation of Different Mobility Models in Disaster Scenarios","authors":"G. Walunjkar, A. Koteswara Rao","doi":"10.1109/RTEICT46194.2019.9016893","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016893","url":null,"abstract":"Peoples trapped in the disastrous areas may have chances to survive if they are rescued in seventy two hours. Ad hoc networks are considered more suitable for such scenarios due to infrastructure-less feature. Two different mobility models - Reference group Mobility Model and Disaster Area Model are generally used in such scenario. In this paper, various ad hoc routing protocols such as destination distance vector routing protocol, dynamic source routing protocol, ad hoc on demand routing protocol and ad hoc on demand multipath routing protocol are discussed and analyzed using reference group mobility models and disaster area model. Also these protocols are compared using various performance metrics such as packet delivery ratio, delay, throughput, control overhead, average energy consumed etc.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122287645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016882
Shrinidhi N Bagewadi, Syed Shadab, J. Roopa
Memories constitute a major portion of any system on chip(SoC). As the density in the SoC is increasing, the requirement on increased size of memories present also increasing. Testing of such large memories becomes an increasingly challenging task. Memory Built-in self-test (MBIST) is a built in self-test used for memories conventionally, which is used to verify the functionality of the memory and detect faults in the memory arrays. With the pace of growing technology, time to market plays an important role for any product and thus this leads to demand for optimizing MBIST mechanism for faster validation of memories. Increasing the frequency of operation is not an option as it might disturb signatures in the memory. Also, due to large amount of memory present, it becomes time consuming to test every bit of memory on SoC. In this paper, it is shown to reduce the test time for the memories at pre-silicon stage. Thus, a novel Fast BIST mechanism is proposed that uses selective testing of memories in the array which uses sampling method for testing the memories. Using this mechanism reduces testing time significantly. Thus this can be used in pre-silicon stages of SoC as well as for tests that may not require full memory scan. When Fast BIST is implemented on a memory array of 32x4096 for 50% of addresses at 500MHz test frequency, we can achieve as high as 31.01% reduction in testing time by running tests over limited addresses. Similarly we can achieve 56% improvement for 10% addresses.
存储器构成了任何片上系统(SoC)的主要部分。随着SoC中密度的增加，对存储器尺寸的要求也在增加。测试如此大的内存成为一项越来越具有挑战性的任务。内存内置自检(Memory built -in self-test, MBIST)是传统上用于内存的内建自检，用于验证内存的功能和检测内存阵列的故障。随着技术的发展，上市时间对任何产品都起着重要的作用，因此这导致了对优化MBIST机制以更快地验证存储器的需求。不能增加操作的频率，因为它可能会干扰内存中的签名。此外，由于存在大量内存，测试SoC上的每个内存位变得非常耗时。本文的研究表明，这种方法可以减少存储器在预硅阶段的测试时间。在此基础上，提出了一种采用采样法对阵列中的存储器进行选择性测试的快速BIST机制。使用这种机制可以显著减少测试时间。因此，这可以用于SoC的预硅阶段以及可能不需要全内存扫描的测试。当在32x4096的存储器阵列上以500MHz测试频率为50%的地址实现Fast BIST时，通过在有限的地址上运行测试，我们可以实现高达31.01%的测试时间减少。同样，对于10%的地址，我们可以实现56%的改进。
{"title":"Fast BIST Mechanism for Faster Validation of Memory Array","authors":"Shrinidhi N Bagewadi, Syed Shadab, J. Roopa","doi":"10.1109/RTEICT46194.2019.9016882","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016882","url":null,"abstract":"Memories constitute a major portion of any system on chip(SoC). As the density in the SoC is increasing, the requirement on increased size of memories present also increasing. Testing of such large memories becomes an increasingly challenging task. Memory Built-in self-test (MBIST) is a built in self-test used for memories conventionally, which is used to verify the functionality of the memory and detect faults in the memory arrays. With the pace of growing technology, time to market plays an important role for any product and thus this leads to demand for optimizing MBIST mechanism for faster validation of memories. Increasing the frequency of operation is not an option as it might disturb signatures in the memory. Also, due to large amount of memory present, it becomes time consuming to test every bit of memory on SoC. In this paper, it is shown to reduce the test time for the memories at pre-silicon stage. Thus, a novel Fast BIST mechanism is proposed that uses selective testing of memories in the array which uses sampling method for testing the memories. Using this mechanism reduces testing time significantly. Thus this can be used in pre-silicon stages of SoC as well as for tests that may not require full memory scan. When Fast BIST is implemented on a memory array of 32x4096 for 50% of addresses at 500MHz test frequency, we can achieve as high as 31.01% reduction in testing time by running tests over limited addresses. Similarly we can achieve 56% improvement for 10% addresses.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130555104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016983
Sushma. M. Gowda, D. K. Rahul, A. Anand, S. Veena, V. B. Durdi
Voice Controlled MAV (Micro Air Vehicle) is an attractive alternative to flying the MAVs without a joystick/ mouse clicks. This being a command and control application calls for accurate and fast Speech Recognition. The paper proposes a feed forward neural network based speech recognition for voice controlled MAV application, which achieves better accuracy and faster recognition compared Viterbi algorithm which operates on statistical data. ANN (Artificial Neural Network) could achieve word accuracy of 93% against 85% as achieved by HMM (Hidden Markov Model). ANN achieved about 25% faster recognition compared to HMM.
{"title":"Artificial Neural Network based Automatic Speech Recognition Engine for Voice Controlled Micro Air Vehicles","authors":"Sushma. M. Gowda, D. K. Rahul, A. Anand, S. Veena, V. B. Durdi","doi":"10.1109/RTEICT46194.2019.9016983","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016983","url":null,"abstract":"Voice Controlled MAV (Micro Air Vehicle) is an attractive alternative to flying the MAVs without a joystick/ mouse clicks. This being a command and control application calls for accurate and fast Speech Recognition. The paper proposes a feed forward neural network based speech recognition for voice controlled MAV application, which achieves better accuracy and faster recognition compared Viterbi algorithm which operates on statistical data. ANN (Artificial Neural Network) could achieve word accuracy of 93% against 85% as achieved by HMM (Hidden Markov Model). ANN achieved about 25% faster recognition compared to HMM.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116290944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016921
Harshitha, V. Chaitanya, Shazia M Killedar, Dheeraj Revankar, M. Pushpa
Breast cancer is the most common and a major death causing disease diagnosed among women worldwide. Early detection of this disease can reduce the death rates. Image processing techniques using machine learning are widely used in medical domain to improve the early detection of cancerous tumors in breast. In this proposed approach, supervised learning techniques are used to extract cancer defining features and classify cancerous images from the normal mammogram images. The supervised system is initially trained by extracting 13 features each from a dataset of 30 images. The extracted features of the image under test are associated with the features extracted from the database images to detect and predict the cancer tumor in the image. Support Vector Machine (SVM) and K-Nearest Neighbours(KNN) is used for classification. Based on the analysis, the system is capable to give a classification accuracy of 95%(SVM) and 97% (KNN). A GUI based interface is also developed for the same. Further, a user-friendly chatbot is developed using Dialog Flow, which interacts with patients to predict cancer based on the symptoms identified by the patient. This chatbot can be used by the patient to detect whether the symptoms are porne to cancer.
{"title":"Recognition and Prediction of Breast Cancer using Supervised Diagnosis","authors":"Harshitha, V. Chaitanya, Shazia M Killedar, Dheeraj Revankar, M. Pushpa","doi":"10.1109/RTEICT46194.2019.9016921","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016921","url":null,"abstract":"Breast cancer is the most common and a major death causing disease diagnosed among women worldwide. Early detection of this disease can reduce the death rates. Image processing techniques using machine learning are widely used in medical domain to improve the early detection of cancerous tumors in breast. In this proposed approach, supervised learning techniques are used to extract cancer defining features and classify cancerous images from the normal mammogram images. The supervised system is initially trained by extracting 13 features each from a dataset of 30 images. The extracted features of the image under test are associated with the features extracted from the database images to detect and predict the cancer tumor in the image. Support Vector Machine (SVM) and K-Nearest Neighbours(KNN) is used for classification. Based on the analysis, the system is capable to give a classification accuracy of 95%(SVM) and 97% (KNN). A GUI based interface is also developed for the same. Further, a user-friendly chatbot is developed using Dialog Flow, which interacts with patients to predict cancer based on the symptoms identified by the patient. This chatbot can be used by the patient to detect whether the symptoms are porne to cancer.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125612525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016923
N. S. Sumana, B. Sahana, Abhay Deshapande
This paper proposes a mixed logic design technique for implementation of low power - high speed line decoders. Mixed logic design method combines Pass transistor- Dual Value Logic (DVL), Transmission Gate Logic(TGL) and Static CMOS logic. 2–4 decoders are implemented using two novel topologies, a 14-transistor low power topology for reducing power and a 15-transistor high performance topology for minimizing delay and power dissipation with reduced number of transistors in each case. In each case both non-inverting and inverting decoders are implemented, thus providing a total of four new decoder designs. 4–16 decoders are implemented using 2–4 mixed logic pre-decoders and CMOS post-decoder. Mixed logic decoders provide full-swung capability. Furthermore, all the proposed 2–4 decoders are implemented with enable input, this design eliminates the CMOS post decoder and provides a complete mixed logic 4–16 decoder. All the proposed decoders are implemented using Cadence Virtuoso tool in 180nm technology and the simulation results prove that the mixed logic decoders provide a significant improvement in power and delay with reduced number of transistors, outperforming conventional CMOS decoders in almost all cases.
{"title":"Design and Implementation of Low Power - High Performance Mixed Logic Line Decoders","authors":"N. S. Sumana, B. Sahana, Abhay Deshapande","doi":"10.1109/RTEICT46194.2019.9016923","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016923","url":null,"abstract":"This paper proposes a mixed logic design technique for implementation of low power - high speed line decoders. Mixed logic design method combines Pass transistor- Dual Value Logic (DVL), Transmission Gate Logic(TGL) and Static CMOS logic. 2–4 decoders are implemented using two novel topologies, a 14-transistor low power topology for reducing power and a 15-transistor high performance topology for minimizing delay and power dissipation with reduced number of transistors in each case. In each case both non-inverting and inverting decoders are implemented, thus providing a total of four new decoder designs. 4–16 decoders are implemented using 2–4 mixed logic pre-decoders and CMOS post-decoder. Mixed logic decoders provide full-swung capability. Furthermore, all the proposed 2–4 decoders are implemented with enable input, this design eliminates the CMOS post decoder and provides a complete mixed logic 4–16 decoder. All the proposed decoders are implemented using Cadence Virtuoso tool in 180nm technology and the simulation results prove that the mixed logic decoders provide a significant improvement in power and delay with reduced number of transistors, outperforming conventional CMOS decoders in almost all cases.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125997018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016943
G. Spoorthi, M. B. Akkamahadevi
5G networks are the next generation of mobile internet connectivity. Mobile data traffic may reach 30 Exabyte's per month. Microwave bands may reach saturation state to deliver the increment of data rate. Millimeter(mmwave) band is a promising band between 30 to 300 GHz. The main advantages of mmwave band are its small antenna radius and high attenuation. Handover in 5G mmwave is challenging because of its short cell radius where user equipment may perform a greater number of handovers meanwhile increasing handover delay. This paper presents the work of modification of x2 handover mechanism in 5G mmwave network. It mainly deals with reducing handover delay in 5G mmwave network considering different trajectories such as Horizontal trajectory and combination of horizontal and vertical.
{"title":"Handover Mechanism in 5G mmwave Band","authors":"G. Spoorthi, M. B. Akkamahadevi","doi":"10.1109/RTEICT46194.2019.9016943","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016943","url":null,"abstract":"5G networks are the next generation of mobile internet connectivity. Mobile data traffic may reach 30 Exabyte's per month. Microwave bands may reach saturation state to deliver the increment of data rate. Millimeter(mmwave) band is a promising band between 30 to 300 GHz. The main advantages of mmwave band are its small antenna radius and high attenuation. Handover in 5G mmwave is challenging because of its short cell radius where user equipment may perform a greater number of handovers meanwhile increasing handover delay. This paper presents the work of modification of x2 handover mechanism in 5G mmwave network. It mainly deals with reducing handover delay in 5G mmwave network considering different trajectories such as Horizontal trajectory and combination of horizontal and vertical.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115914797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016855
V. Balaji, Ch.K.S.D. Ranga, N. Shylashree, N. Praveena
This paper describes the design and implementation of an embedded ROM memory along with its sense amplifier. Several applications in machine learning have fixed data to be stored in a memory, which needs to be read out multiple times. Hence a fast, on-chip solution is proposed in this technical paper wherein logic transistors are used to design a read only memory with completely zero added process complexity. Several design constraints of sensing the ROM cell have been elaborated to a great extent. Also, a key advantage in the sense amplifier used is the ability to use all transistors from the same process technology. Further, by always fixing a MOS device in saturation and the other MOS device in cut off region, fast sensing is achieved at the sense amplifier output. The layout designed for the sense amplifier is verified to produce a very minimal deviation from the actual schematic simulations, hence suggesting a considerably well designed layout. The operating frequency of the sense amplifier is determined as 12.5 GHz with full swing resolution.
{"title":"Design of a Delta Threshold Voltage Difference based fully Embedded Read Only Memory along with a Skew Sense Amplifier","authors":"V. Balaji, Ch.K.S.D. Ranga, N. Shylashree, N. Praveena","doi":"10.1109/RTEICT46194.2019.9016855","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016855","url":null,"abstract":"This paper describes the design and implementation of an embedded ROM memory along with its sense amplifier. Several applications in machine learning have fixed data to be stored in a memory, which needs to be read out multiple times. Hence a fast, on-chip solution is proposed in this technical paper wherein logic transistors are used to design a read only memory with completely zero added process complexity. Several design constraints of sensing the ROM cell have been elaborated to a great extent. Also, a key advantage in the sense amplifier used is the ability to use all transistors from the same process technology. Further, by always fixing a MOS device in saturation and the other MOS device in cut off region, fast sensing is achieved at the sense amplifier output. The layout designed for the sense amplifier is verified to produce a very minimal deviation from the actual schematic simulations, hence suggesting a considerably well designed layout. The operating frequency of the sense amplifier is determined as 12.5 GHz with full swing resolution.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133887748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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