A review on power optimized TPG using LP-LFSR for low power BIST

Abstract

The main challenging areas in VLSI are performance, cost, and power dissipation. The demand for portable computing devices and communications system are increasing rapidly. These applications require low power dissipation VLSI circuits. The power dissipation during test mode is 200% more than in normal mode. This research article proposed a logic BIST using low power linear feedback shift register (LFSR) to generate low power test patterns. The designed architecture is programmed using VHDL and simulated using free active HDL tool. The experimental results demonstrate significant power reduction by low power TPG than compared to standard LFSR.