{"title":"High Speed-Low Power GNRFET based Digital to Analog Converters for ULSI applications","authors":"Mounica Patnala, T. Ytterdal, M. Rizkalla","doi":"10.1109/NAECON46414.2019.9057977","DOIUrl":null,"url":null,"abstract":"In this papr, A 2-bit, 3-bit, and 4-bit DACs using newly emerged transistor technology known as Graphene Nano Ribbon Field Effect Transistor (GNRFET) technology were developed. A channel length of 10nm for the GNRFET device with supply voltage of 0.7V was incorporated in the design and simulated via ADS (Advanced Digital System) platform. Biasing with current mirror topology was used for highly efficient small size implementation. The power consumption was analyzed for all three devices. The design showed a full range linear input region within the 0.7 V supply. The signal to noise distortion ratio (SNDR) was 25.8 for the 4-bit DAC. The findings of this design conclude that the proposed DAC is more suitable for high speed nano electromechanical systems (NEMs), computer architecture and memory cells, among other applications.","PeriodicalId":193529,"journal":{"name":"2019 IEEE National Aerospace and Electronics Conference (NAECON)","volume":"2008 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE National Aerospace and Electronics Conference (NAECON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NAECON46414.2019.9057977","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this papr, A 2-bit, 3-bit, and 4-bit DACs using newly emerged transistor technology known as Graphene Nano Ribbon Field Effect Transistor (GNRFET) technology were developed. A channel length of 10nm for the GNRFET device with supply voltage of 0.7V was incorporated in the design and simulated via ADS (Advanced Digital System) platform. Biasing with current mirror topology was used for highly efficient small size implementation. The power consumption was analyzed for all three devices. The design showed a full range linear input region within the 0.7 V supply. The signal to noise distortion ratio (SNDR) was 25.8 for the 4-bit DAC. The findings of this design conclude that the proposed DAC is more suitable for high speed nano electromechanical systems (NEMs), computer architecture and memory cells, among other applications.
本文采用新型晶体管技术石墨烯纳米带场效应晶体管(GNRFET)技术开发了2位、3位和4位dac。设计中引入了电源电压为0.7V、通道长度为10nm的GNRFET器件,并通过ADS (Advanced Digital System)平台进行了仿真。采用电流镜像拓扑进行偏置,实现了高效率的小尺寸实现。对这三种设备的功耗进行了分析。该设计显示了0.7 V电源内的全范围线性输入区域。4位DAC的信噪比(SNDR)为25.8。本设计的研究结果表明,所提出的DAC更适合高速纳米机电系统(nem)、计算机体系结构和存储单元等应用。