Exploiting fault tolerance within cache memory structures

Abstract

Cache memories can work as buffer between processors and main memories. It enables rapid access of data for a processor in operation. Set-associativity provides optimality in mapping of cache memories and reduction of cache miss probability. Design of a high speed cache has always been a desirable criteria of hardware experts as it increases processor utilization. Exploiting fault tolerance within such a cache memory of higher throughput ensures reliable data transfer and is an open research problem in the domain of high-performance computing. This paper proposes a design of low-order interleaved set-associative cache memory with lesser response time and exploits a high degree of fault tolerance.