B. Perumana, J. Zhan, S. S. Taylor, B. Carlton, J. Laskar
{"title":"A 9.2 mW, 4-8 GHz Resistive Feedback CMOS LNA with 24.4 dB Gain, 2 dB Noise Figure, and 21.5 dBm Output IP3","authors":"B. Perumana, J. Zhan, S. S. Taylor, B. Carlton, J. Laskar","doi":"10.1109/SMIC.2008.15","DOIUrl":null,"url":null,"abstract":"A 9.2 mW resistive feedback CMOS low-noise amplifier with a 3-dB bandwidth of 3.94 GHz (4.04 -7.98 GHz) is presented. At 5.5 GHz, the fully integrated LNA achieves a measured gain above 24 dB, a noise figure of 2 dB, and an output IP3 of 21.5 dBm. The LNA draws 7.7 mA from the 1.2 V supply and utilizes a single compact low-Q on-chip inductor. The LNA is implemented in a 90-nm CMOS process and occupies a die area of only 0.022 mm2.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMIC.2008.15","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
A 9.2 mW resistive feedback CMOS low-noise amplifier with a 3-dB bandwidth of 3.94 GHz (4.04 -7.98 GHz) is presented. At 5.5 GHz, the fully integrated LNA achieves a measured gain above 24 dB, a noise figure of 2 dB, and an output IP3 of 21.5 dBm. The LNA draws 7.7 mA from the 1.2 V supply and utilizes a single compact low-Q on-chip inductor. The LNA is implemented in a 90-nm CMOS process and occupies a die area of only 0.022 mm2.