Stacked Keeper with Body Bias Approach to Reduce Leakage Power for 2-Byte CAM Using 180NM CMOS Technology

Abstract

Over the past few decades, the designers concentrating on different techniques to design low power chips. The power consumption can be reduced by minimizing the leakage power and leakage current in that specified design. Power consumption is main criteria in digital memory circuits, to reduce and to recover the power, we have many techniques are available. A Stacked Keeper Body Bias (SKBB) is one of the technique is applied to the conditional circuitry of the memory block. The modification and replacements were done in the conditional circuitry. The Bit Line, Write Line decoder, Priority Encoder was used to design efficient 2Byte CAM. The result shows that it is dissipating 50% less power than the conventional CAM Design.