Optimum windows of DRAM input impedance (Lin,Cin,Rin) on data bus for 800 MHz signaling

Abstract

This paper describes a methodology to analyze a long periodic channel. The work was performed for the RAMBUS system. The analysis is focused on DRAM loading effects on electrical signal integrity. We suggest some proper windows of DRAM input impedance for 800 MHz signaling. Without additional constraints to /spl Delta/Lin (pin-to-pin Lin differences), the skew amounts to 45 ps, which can be lowered to 22 ps by the control of /spl Delta/Lin within 1.5 nH.