Design Of A Parallel Bus-to-Scan Test Port Converter

Abstract

The IEEE Std. 1149.1 Standard Test Access Port and Boundary-Scan Architecture [1] as well as other scan path methodologies use a serial interface for transmitting data to and from the circuit under test. This serial communication presents an efficiency problem in transferring data between a processor and the scan ring. This paper describes the architecture and features of a device that interfaces a parallel host bus to a serial test bus. The Parallel/Serial (P/S) Converter integrates several features to simplify board test and offers a way to make scan operations more efficient by managing shift operations directly in hardware.