Design of an embedded CMOS CR SAR ADC for low power applications in bio-sensor SOC

Abstract

This paper presents a Charge Redistribution Successive Approximation Register ADC designed in a 0.35-mum standard CMOS process. The total power consumption is only 4.6 mW, and a resolution of 10 bits is achieved. The ADC maintains a maximum DNL of less than 0.4 LSB, an INL less than 0.5 LSB, and an ENOB of 9.9 bits. It can be integrated with micro-sensors to monolithically form highly sensitive, reliable and intelligent measurement devices.