Effects of package stackups on microprocessor performance

Abstract

Three multi-layer stackups are analyzed for ceramic packages with solid planes and thin substrates. The advantages and disadvantages of using decoupling capacitors for high performance applications are also analyzed. This paper shows how different package stackups, number of power and ground planes, and the number of routing layers affect the performance of the packaging device and subsequently the current consumption demanded by the simultaneously switching drivers and core logic on the microprocessor. A multi-layer ceramic package with solid planes and thin substrates is analyzed to provide a complete characterization of the system made of drivers, core logic, package, and motherboard. Such analysis serves as a basic building block for setting a criteria on different package designs.