Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838877
Tom Chen, A. Andrews, A. Hajjar, Charles Anderson, M. Sahinoglu
When designing a system in the behavioral level, one of the most important steps to be taken is verifying its functionality before it is released to the logic/PD design phase. One may consider behavioral models as oracles in industries to test against when the final chip is produced. In this work, we use branch coverage as a measure for the quality of verifying/testing behavioral models. Minimum effort for achieving a given quality level can be realized by using the proposed stopping rule. The stopping rule guides the process to switch to a different testing strategy using different types of patterns, i.e. random vs. functional, or using different set of parameters to generate patterns/test cases, when the current strategy is expected not to increase the coverage. We demonstrate the use of the stopping rule on two complex behavioral level VHDL models that were tested for branch coverage with 4 different testing phases. We compare savings of the number of applied testing patterns and quality of testing both with and without using the stopping rule, and show that switching phases at certain points guided by the stopping rule would yield to the same or even better coverage with less number of testing patterns.
{"title":"Achieving the quality of verification for behavioral models with minimum effort","authors":"Tom Chen, A. Andrews, A. Hajjar, Charles Anderson, M. Sahinoglu","doi":"10.1109/ISQED.2000.838877","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838877","url":null,"abstract":"When designing a system in the behavioral level, one of the most important steps to be taken is verifying its functionality before it is released to the logic/PD design phase. One may consider behavioral models as oracles in industries to test against when the final chip is produced. In this work, we use branch coverage as a measure for the quality of verifying/testing behavioral models. Minimum effort for achieving a given quality level can be realized by using the proposed stopping rule. The stopping rule guides the process to switch to a different testing strategy using different types of patterns, i.e. random vs. functional, or using different set of parameters to generate patterns/test cases, when the current strategy is expected not to increase the coverage. We demonstrate the use of the stopping rule on two complex behavioral level VHDL models that were tested for branch coverage with 4 different testing phases. We compare savings of the number of applied testing patterns and quality of testing both with and without using the stopping rule, and show that switching phases at certain points guided by the stopping rule would yield to the same or even better coverage with less number of testing patterns.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116910977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838920
A. Nardi, A. Neviani, C. Guardiani
A new algorithm to determine the number and value of realistic worst-case models for the performance of module library components is presented in this paper. The proposed algorithm employs principal components analysis (PCA) at the performance level to identify the main independent sources of variance for the performance of a set of library modules. Response surfaces methodology (RSM) and propagation of variance (POV) based algorithms are used to efficiently compute the performance level covariance matrix and nonlinear maximum likelihood optimization to trace back worst case models at the SPICE level. The effectiveness of the proposed methodology has been demonstrated by determining a realistic set of worst case models for a 0.25 /spl mu/m CMOS standard cell library.
{"title":"Realistic worst-case modeling by performance level principal component analysis","authors":"A. Nardi, A. Neviani, C. Guardiani","doi":"10.1109/ISQED.2000.838920","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838920","url":null,"abstract":"A new algorithm to determine the number and value of realistic worst-case models for the performance of module library components is presented in this paper. The proposed algorithm employs principal components analysis (PCA) at the performance level to identify the main independent sources of variance for the performance of a set of library modules. Response surfaces methodology (RSM) and propagation of variance (POV) based algorithms are used to efficiently compute the performance level covariance matrix and nonlinear maximum likelihood optimization to trace back worst case models at the SPICE level. The effectiveness of the proposed methodology has been demonstrated by determining a realistic set of worst case models for a 0.25 /spl mu/m CMOS standard cell library.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116235344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838879
A. Hunter, C. Lau, J. Martin
Recent advances in process and integration are enabling systems level integration for numerous applications. The quality of the systems depends directly on the quality of the processes and effectiveness of the process integration, and on the quality of the designs and libraries employed, as well as on the completeness and accuracy of the models used to link the process and designs. Unit process and process module quality is ensured through the use of designed experimentation, margin analysis, and statistical capability measurement. The link between the processes and the libraries and designs is formed through such models as SPICE and interconnect, with quality implications associated with the extraction and implementation. GDSII algorithms to incorporate process specific post layout features such as OPC and fill patterns for CMP planarization are integrated into the CAD flow prior to final verification, reticle manufacturing and silicon prototyping. Foundry specific challenges in providing process and library elements include multiple design flows, tool providers and library suppliers. Examples of approaches to quality designs, processes and systems are presented using advanced cores and systems level integration.
{"title":"Combining advanced process technology and design for systems level integration","authors":"A. Hunter, C. Lau, J. Martin","doi":"10.1109/ISQED.2000.838879","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838879","url":null,"abstract":"Recent advances in process and integration are enabling systems level integration for numerous applications. The quality of the systems depends directly on the quality of the processes and effectiveness of the process integration, and on the quality of the designs and libraries employed, as well as on the completeness and accuracy of the models used to link the process and designs. Unit process and process module quality is ensured through the use of designed experimentation, margin analysis, and statistical capability measurement. The link between the processes and the libraries and designs is formed through such models as SPICE and interconnect, with quality implications associated with the extraction and implementation. GDSII algorithms to incorporate process specific post layout features such as OPC and fill patterns for CMP planarization are integrated into the CAD flow prior to final verification, reticle manufacturing and silicon prototyping. Foundry specific challenges in providing process and library elements include multiple design flows, tool providers and library suppliers. Examples of approaches to quality designs, processes and systems are presented using advanced cores and systems level integration.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130296293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838899
Li-Fu Chang, Keh-Jeng Chang, Christopher J. Bianchi
Skin effects should be considered for accurate deep-submicron (DSM, 0.35 /spl mu/m and below) interconnect modeling. Conventionally the sheet-/spl rho/ for uniform or plasma-etched conductors is reasonably constant, so the frequency-dependent skin effect can be found by straightforward field simulations, which require sheet-/spl rho/ being constant. In that case, the skin-depth is primarily function of harmonic frequency and the environment. However, for damascene-processed conductors, the sheet-/spl rho/ is function of line width. Therefore, the impedance (resistance and inductance in this paper) has to be determined by field solvers using a new methodology we propose in this paper. For each DSM technology, sets of interconnect structures with comprehensive range of line widths and neighbors for each metal level are provided and simulated in advance. In this way, a library for each DSM technology is available for accurate and efficient VLSI interconnect modeling.
{"title":"A proposal for accurately modeling frequency-dependent on-chip interconnect impedance","authors":"Li-Fu Chang, Keh-Jeng Chang, Christopher J. Bianchi","doi":"10.1109/ISQED.2000.838899","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838899","url":null,"abstract":"Skin effects should be considered for accurate deep-submicron (DSM, 0.35 /spl mu/m and below) interconnect modeling. Conventionally the sheet-/spl rho/ for uniform or plasma-etched conductors is reasonably constant, so the frequency-dependent skin effect can be found by straightforward field simulations, which require sheet-/spl rho/ being constant. In that case, the skin-depth is primarily function of harmonic frequency and the environment. However, for damascene-processed conductors, the sheet-/spl rho/ is function of line width. Therefore, the impedance (resistance and inductance in this paper) has to be determined by field solvers using a new methodology we propose in this paper. For each DSM technology, sets of interconnect structures with comprehensive range of line widths and neighbors for each metal level are provided and simulated in advance. In this way, a library for each DSM technology is available for accurate and efficient VLSI interconnect modeling.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126935027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838875
T. Bautista, A. Núñez
A complete quantitative evaluation of the quality of more than one hundred implementations of SPARC processor core and its related circuitry, synthesized from VHDL descriptions, is presented in this paper as a demonstration example for selecting benchmark circuits, synthesis experiments with different tools and technologies, and performance metrics, for evaluating the quality of IP blocks and megacells. The methodology of the experiments conducted for these circuits can be applied to a wide range of other benchmark candidate circuits. The synthesis experiments are designed to fully explore the synthesis space and to analyze the impact of every synthesis step on the final design quality obtained.
{"title":"Synthesis experiments and performance metrics for evaluating the quality of IP blocks and megacells","authors":"T. Bautista, A. Núñez","doi":"10.1109/ISQED.2000.838875","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838875","url":null,"abstract":"A complete quantitative evaluation of the quality of more than one hundred implementations of SPARC processor core and its related circuitry, synthesized from VHDL descriptions, is presented in this paper as a demonstration example for selecting benchmark circuits, synthesis experiments with different tools and technologies, and performance metrics, for evaluating the quality of IP blocks and megacells. The methodology of the experiments conducted for these circuits can be applied to a wide range of other benchmark candidate circuits. The synthesis experiments are designed to fully explore the synthesis space and to analyze the impact of every synthesis step on the final design quality obtained.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127038332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838857
Lifeng Wu, Jingkun Fang, H. Yan, Ping Chen, A. Chen, Y. Okamoto, C. Yeh, Zhihong Liu, N. Iwanishi, N. Koike, H. Yonezawa, Y. Kawakami
Gate level circuit simulation on hot carrier degradation is introduced for the first time by the GLACIER system presented in this paper. The inherent advantages such as high speed and high capacity of the gate level simulation as compared to the traditional transistor level hot carrier simulation makes the design-in reliability simulation possible and practical for the deep submicron VLSI circuit designs with millions of transistors. By virtue of a unique ratio based modeling technique, GLACIER system provides a very high accuracy which is mostly within 1% difference of transistor level hot carrier simulation.
{"title":"GLACIER: a hot carrier gate level circuit characterization and simulation system for VLSI design","authors":"Lifeng Wu, Jingkun Fang, H. Yan, Ping Chen, A. Chen, Y. Okamoto, C. Yeh, Zhihong Liu, N. Iwanishi, N. Koike, H. Yonezawa, Y. Kawakami","doi":"10.1109/ISQED.2000.838857","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838857","url":null,"abstract":"Gate level circuit simulation on hot carrier degradation is introduced for the first time by the GLACIER system presented in this paper. The inherent advantages such as high speed and high capacity of the gate level simulation as compared to the traditional transistor level hot carrier simulation makes the design-in reliability simulation possible and practical for the deep submicron VLSI circuit designs with millions of transistors. By virtue of a unique ratio based modeling technique, GLACIER system provides a very high accuracy which is mostly within 1% difference of transistor level hot carrier simulation.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130611888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838895
A. Walker, P. Lala
A new mixed-signal built-in self-test approach that is based upon voltage transitions at the primary output of the analog block under test (CUT) is presented in this paper. This CUT output is the pulse response of the CUT for a rail-to-rail pulse stream. The technique can effectively detect both soft and hard faults and does not require an analog-to-digital converter (ADC) or/and digital-to-analog converter (DAC). This approach also does not require any additional analog circuits to realize the test signal generator and sample circuits. The paper is concluded with an example of the application of the proposed approach for a passive second order notch filter.
{"title":"A transition based BIST approach for passive analog circuits","authors":"A. Walker, P. Lala","doi":"10.1109/ISQED.2000.838895","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838895","url":null,"abstract":"A new mixed-signal built-in self-test approach that is based upon voltage transitions at the primary output of the analog block under test (CUT) is presented in this paper. This CUT output is the pulse response of the CUT for a rail-to-rail pulse stream. The technique can effectively detect both soft and hard faults and does not require an analog-to-digital converter (ADC) or/and digital-to-analog converter (DAC). This approach also does not require any additional analog circuits to realize the test signal generator and sample circuits. The paper is concluded with an example of the application of the proposed approach for a passive second order notch filter.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130773453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838861
M. Keating
Chips continue to get larger and more complex, and as they do, design quality continues to become more difficult and more important. Improving quality metrics is a key to addressing this problem, both for measuring quality and for predicting design quality early in the design cycle. This paper proposes a method of quantifying design complexity, enabling design teams to produce architectures and implementations that manage complexity, and hence quality, effectively.
{"title":"Measuring design quality by measuring design complexity","authors":"M. Keating","doi":"10.1109/ISQED.2000.838861","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838861","url":null,"abstract":"Chips continue to get larger and more complex, and as they do, design quality continues to become more difficult and more important. Improving quality metrics is a key to addressing this problem, both for measuring quality and for predicting design quality early in the design cycle. This paper proposes a method of quantifying design complexity, enabling design teams to produce architectures and implementations that manage complexity, and hence quality, effectively.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130938971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838880
C. Duvvury
ESD is a major concern for IC chip quality both from building-in-reliability requirement and from long-term field operation requirement. The damage phenomena, either from human handling or machine contact, could appear as thermal damage and oxide rupture. In this paper, the IC damage phenomena due to ESD, the effects on the IC functionality, the proper methods to overcome these with on-chip protection designs, and the challenges facing these protection methods with the advanced process and package technologies are presented. Simulation and modeling methods that are currently used to improve the protection designs are also reviewed.
{"title":"ESD: design for IC chip quality and reliability","authors":"C. Duvvury","doi":"10.1109/ISQED.2000.838880","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838880","url":null,"abstract":"ESD is a major concern for IC chip quality both from building-in-reliability requirement and from long-term field operation requirement. The damage phenomena, either from human handling or machine contact, could appear as thermal damage and oxide rupture. In this paper, the IC damage phenomena due to ESD, the effects on the IC functionality, the proper methods to overcome these with on-chip protection designs, and the challenges facing these protection methods with the advanced process and package technologies are presented. Simulation and modeling methods that are currently used to improve the protection designs are also reviewed.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127968025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-20DOI: 10.1109/ISQED.2000.838935
B. Franzini, C. Forzan, D. Pandini, Primo Scandolara, A. Fabbro
Interconnect parasitic effects are one of the limiting factors for the performances of deep submicron VLSI designs, where the interconnect induced delay, dominates over the gate delay. Furthermore, as coupling capacitance between wires increases due to the geometry scaling, the design verification process must accurately take into account crosstalk induced effects. In this paper, we describe CASTA (Crosstalk Aware Static Timing Analysis), a new efficient and accurate methodology for the timing performance verification of large VLSI designs, which accurately considers the crosstalk induced delay and noise injection. Our approach is based on the combination of Static Timing Analysis (STA) with interconnect network order reduction macromodeling techniques and it allows us to evaluate the crosstalk effects during gate-level delay calculation, thus enlightening potential timing hazards. The timing effects due to the crosstalk between adjacent interconnects are accounted by a order reduction based macromodel of the overall linear interconnect network. The effectiveness of the proposed methodology has been demonstrated with the analysis of the crosstalk effects on a 0.25 /spl mu/m, high density CMOS technology.
{"title":"Crosstalk aware static timing analysis: a two step approach","authors":"B. Franzini, C. Forzan, D. Pandini, Primo Scandolara, A. Fabbro","doi":"10.1109/ISQED.2000.838935","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838935","url":null,"abstract":"Interconnect parasitic effects are one of the limiting factors for the performances of deep submicron VLSI designs, where the interconnect induced delay, dominates over the gate delay. Furthermore, as coupling capacitance between wires increases due to the geometry scaling, the design verification process must accurately take into account crosstalk induced effects. In this paper, we describe CASTA (Crosstalk Aware Static Timing Analysis), a new efficient and accurate methodology for the timing performance verification of large VLSI designs, which accurately considers the crosstalk induced delay and noise injection. Our approach is based on the combination of Static Timing Analysis (STA) with interconnect network order reduction macromodeling techniques and it allows us to evaluate the crosstalk effects during gate-level delay calculation, thus enlightening potential timing hazards. The timing effects due to the crosstalk between adjacent interconnects are accounted by a order reduction based macromodel of the overall linear interconnect network. The effectiveness of the proposed methodology has been demonstrated with the analysis of the crosstalk effects on a 0.25 /spl mu/m, high density CMOS technology.","PeriodicalId":113766,"journal":{"name":"Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131691288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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